VNC2 参数 Datasheet PDF下载

Document No.: FT_000138

VINCULUM-II EMBEDDED DUAL USB HOST CONTROLLER IC Datasheet

Version -

1.0

Clearance No.: FTDI#

143

6.3 Serial Peripheral Interface – Slave

CLK

SS#

External - SPI Master

MOSI

MISO

VNC2 - SPI Slave

Figure 6-4 SPI Slave block diagram

VNC2 has two SPI Slave modules both of which use four wire interfaces: MOSI, MISO, CLK and SS#.

Their main purpose is to send data from main memory to the attached SPI master, and / or receive data

and send it to main memory. The SPI Slave is controlled by the internal CPU using internal memory

mapped I/O registers. It operates from the main system clock, although sampling of input data and

transmission of output data is controlled by the SPI clock (CLK). An SPI transfer can only be initiated by

the SPI Master and begins with the slave select signal being asserted. This is followed by a data byte

being clocked out with the master supplying CLK. The master always supplies the first byte, which is

called a command byte. After this the desired number of data bytes are transferred before the

transaction is terminated by the master de-asserting slave select. An SPI Master is able to abort a

transfer at any time by de-asserting its SS# output. This will cause the Slave to end its current transfer

and return to idle state.

6.3.1 SPI Slave Signal Descriptions

64 Pin

Package

Available

pins

11, 15,

19, 24,

28, 39,

43, 47,

51, 57,

61

12, 16,

20, 25,

29, 40,

44, 48,

52, 58,

62

12,16,

21, 32,

36, 42,

46

12, 24,

30

spi_s0_mosi

Mater Out Slave In

spi_s1_mosi

Input

Synchronous data from master to slave

11, 15,

20, 31,

35, 41,

45

11, 23

29

spi_s1_clk

Input

Slave clock input

48 Pin

Package

Available

pins

32 Pin

Package

Available

pins

spi_s0_clk

Name

Type

Description

13, 17,

22, 26,

31, 41,

45, 49,

55, 59,

13, 18,

22, 33,

37, 43,

47

14, 25,

31

spi_s0_miso

Master In Slave Out

spi_s1_miso

Output

Synchronous data from slave to master

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