Document No.: FT_000138
VINCULUM-II EMBEDDED DUAL USB HOST CONTROLLER IC Datasheet
Version -
1.2
Clearance No.: FTDI#
143
3.12 Pin Configuration Input / Output
VNC2 has multiple interfaces available for connecting to external devices. These are UART, FIFO, SPI
slave, SPI master, GPIO and PWM. The Interface I/O Multiplexer is used to share the available I/O Pins
between each peripheral.
VNC2 is configured with default settings for the I/O pins however they can be easily changed to suit the
needs of a designer. This is explained in
Section 5 – I/O Multiplexer.
Default configuration for each
package type is shown in
The signal names are also indicated for
the VNC1L device as it is pin-compatible with the 48 pin LQFP VNC2 device.
Note: The default value of the pins listed in the following table are only available when the I/O
Mux is enabled. A blank VNC2 chip default is all pins are inputs.
Pin
No.
64
Pin
Pin
No.
48
Pin
Pin
No.
32
Pin
Name
(VINC1-L)
64 Pin
Default
48 Pin
Default
32 PIN
Default
Type
Description
11
11
11
IOBUS0
(BDBUS0)
IOBUS1
(BDBUS1)
IOBUS2
(BDBUS2)
IOBUS3
(BDBUS3)
IOBUS4
(BDBUS4)
IOBUS5
(BDBUS5)
IOBUS6
(BDBUS6)
IOBUS7
(BDBUS7)
IOBUS8
(BCBUS0)
IOBUS9
(BCBUS1)
IOBUS10
(BCBUS2)
IOBUS11
(BCBUS3)
IOBUS12
(ADBUS0)
IOBUS13
(ADBUS1)
IOBUS14
(ADBUS2)
debug_if
debug_if
debug_if
I/O
GPIO
12
12
12
Input
pwm[1]
gpio[A1]
I/O
GPIO
13
13
14
Input
pwm[2]
gpio[A2]
I/O
GPIO
14
14
15
Input
pwm[3]
gpio[A3]
I/O
GPIO
15
15
23
fifo_data[0]
spi_s0_clk
uart_txd
I/O
GPIO
16
16
24
fifo_data[1]
spi_s0_mosi
uart_rxd
I/O
GPIO
17
18
25
fifo_data[2]
spi_s0_miso
uart_rts#
I/O
GPIO
18
19
26
fifo_data[3]
spi_s0_ss#
uart_cts#
I/O
GPIO
19
20
29
fifo_data[4]
spi_m_clk
spi_s0_clk
I/O
GPIO
20
21
30
fifo_data[5]
spi_m_mosi
spi_s0_mosi
I/O
GPIO
22
22
31
fifo_data[6]
spi_m_miso
spi_s0_miso
I/O
GPIO
23
23
32
fifo_data[7]
spi_m_ss_0#
spi_s0_ss#
I/O
GPIO
24
31
-
fifo_rxf#
uart_txd
I/O
GPIO
25
32
-
fifo_txe#
uart_rxd
I/O
GPIO
26
33
-
fifo_rd#
uart_rts#
I/O
GPIO
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