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VNC2-48Q1B-TRAY 参数 Datasheet PDF下载

VNC2-48Q1B-TRAY图片预览
型号: VNC2-48Q1B-TRAY
PDF下载: 下载PDF文件 查看货源
内容描述: [Vinculum-II Embedded Dual USB Host Controller IC]
分类和应用:
文件页数/大小: 88 页 / 2234 K
品牌: FTDI [ FUTURE TECHNOLOGY DEVICES INTERNATIONAL LTD. ]
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Datasheet  
Vinculum-II Embedded Dual USB Host Controller IC  
Version 1.7  
Document No.: FT_000138 Clearance No.: FTDI#143  
5.1 I/O Peripherals Signal Names  
Peripheral  
Signal Name  
Outputs Inputs Description  
Debugger  
debug_if  
uart_txd  
1
1
1
1
1
0
0
0
0
0
8
1
0
0
0
0
1
1
1
1
1
8
debugger interface  
Transmit asynchronous data output  
Request to send control output  
Data acknowledge (data terminal ready control) output  
Enable transmit data for RS485designs  
Receive asynchronous data input  
Clear to sendcontrol input  
uart_rts#  
uart_dtr#  
uart_tx_active  
uart_rxd  
UART  
uart_cts#  
uart_dsr#  
uart_ri#  
Data request (data set ready control) input  
Ring indicator control input  
uart_dcd#  
fifo_data  
Data carrier detect control input  
FIFO data bus  
When high, do not write data into the FIFO. Whenlow,  
data can be written into the FIFO by strobing WR high,  
then low.  
fifo_txe#  
1
0
When high, do not read data fromthe FIFO. Whenlow,  
there is data available in the FIFO which canbe read by  
strobing RD# low, thenhigh.  
Writes the data byte on the D0...D7pins into the  
transmit FIFO bufferwhen WR goesfromhigh to low.  
Enables the current FIFO data byte on D0...D7 whenlow.  
Fetches the next FIFO data byte (if available) fromthe  
receive FIFO buffer whenRD#goesfromhigh to low  
fifo_rxf#  
fifo_wr#  
fifo_rd#  
1
0
0
0
1
1
FIFO  
fifo_oe#  
fifo_clkout  
gpio  
0
0
40  
0
0
1
1
0
0
1
1
1
1
0
1
1
8
1
1
40  
1
1
1
0
1
1
1
0
0
1
1
0
0
0
FIFO output enable synchronous FIFO only  
FIFO clock out synchronous FIFO only  
General purpose I/O  
GPIO  
spi_s0_clk  
spi_s0_ss#  
spi_s0_mosi  
spi_s0_miso  
spi_s1_clk  
spi_s1_ss#  
spi_s1_mosi  
spi_s1_miso  
spi_m_clk  
spi_m_mosi  
spi_m_miso  
spi_m_ss_0#  
spi_m_ss_1#  
pwm  
SPI clock input slave 0  
SPI chip select input slave 0  
SPI masterout serial in slave 0  
SPI master in slave out slave 0  
SPI clock input slave 1  
SPI Slave 0  
SPI chip select input slave 1  
Master out slave in slave 1  
SPI Slave 1  
Master in slave out slave 1  
SPI clock input master  
Master out slave in - master  
SPI Master  
PWM  
Master in slave out - master  
Active low slave select 0 from masterto slave 0  
Active low slave select 1 from masterto slave 1  
Pulse width modulation  
Table 5.1 I/O Peripherals Signal Names  
Note: # is used to indicate an active low signal.  
29  
Copyright © Future Technology Devices International Limited  
 
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