Document Reference No.: FT_000030
Vinculum VNC1L Embedded USB Host Controller IC Datasheet Version 2.01
Clearance No.: FTDI# 50
4
Functional Description
The VNC1L is the first of FTDI’s Vinculum family of Embedded USB host controller integrated circuit
devices. Vinculum can also encapsulate certain USB device classes handling the USB Host Interface and
data transfer functions using the in-built MCU and embedded Flash memory. When interfacing to mass
storage devices, such as USB Flash drives, Vinculum transparently handles the FAT File Structure using a
simple to implement command set. Vinculum provides a cost effective solution for introducing USB host
capability into products that previously did not have the hardware resources to do so.
The VNC1L has a Combined Interface which interfaces a controlling application with the Command
Monitor. The combined interfaces are UART, Parallel FIFO and SPI.
The VNC1L is supplied un-programmed. It can be programmed before assembly or it can be configured
“in the field” with configuration option firmware available from the Vinculum website at
http://www.ftdichip.com.
4.1 Key Features
The VNC1L has the following key features:
•
•
•
•
•
•
•
•
•
•
•
•
Two independent USB Host ports.
8 or 32-bit V-MCU Core.
Dual DMA controllers for hardware acceleration.
64k Embedded Flash Program Memory.
4k internal Data SRAM.
2 x USB 2.0 Slow speed or Full speed Host or Slave ports.
Automatic Low or Full Speed selection.
UART, SPI and Parallel FIFO interfaces.
Up to 28 GPIO pins depending on configuration.
Low power operation (25mA running/2mA standby).
FTDI firmware easily updated in the field.
Multi-processor configuration capable.
4.2 Functional Block Descriptions
The following paragraphs detail each function within VNC1L. Please refer to the block diagram shown in
Figure 2.1
.
USB Transceivers 1 and 2 -
The two USB transceiver cells provide the physical USB device interface
supporting USB 1.1 and USB 2.0 standards. Low-speed and full-speed USB data rates are supported.
Each output driver provides +3.3V level slew rate control signalling, whilst a differential receiver and two
single ended receivers provide USB DATA IN, SE0 and USB Reset condition detection. These cells also
include integrated internal USB pull-up or pull-down resistors as required for host or slave mode.
USB Serial Interface Engine (SIE) -
These blocks handle the parallel to serial and serial to parallel
conversion of the USB physical layer. This includes bit stuffing packets, CRC generation, USB frame
generation and protocol error checking.
12 MHz Oscillator -
The 12MHz Oscillator cell generates a 12MHz reference clock input to the Clock
Multiplier PLL from an external 12MHz crystal.
Clock Multiplier PLL -
The Clock Multiplier PLL takes the 12MHz input from the Oscillator Cell and
generates 24MHz and 48MHz reference clock signals, which are required by the USB SIE Blocks, the MCU
core, System Timer and UART prescalar blocks.
Program and Test Logic -
This block provides a means of programming the onboard E-FLASH memory.
When PROG# is pulled low and the device is reset by pulsing the #RESET low, the onboard E-FLASH
memory is bypassed by an internal hard-coded bootstrap Loader ROM which contains code to allow the E-
Copyright © 2009 Future Technology Devices International Limited
12
FTDI [ FUTURE TECHNOLOGY DEVICES INTERNATIONAL LTD. ]
