Document Reference No.: FT_000017
VDIP2 Vinculum VNC1L Module Datasheet Version 1.0
Clearance No.: FTDI# 145
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3.7.1 Timing Diagram – Parallel FIFO Read Transaction
When in parallel FIFO interface mode, the timing of a read is shown in Figure 3.6 and Table 3.9
Figure 3.6 - FIFO Read Cycle.
Time
Description
Min
Max
Unit
T1
T2
T3
T4
T5
T6
RD# Active Pulse Width
RD# to RD# Pre-Charge Time
RD# Active to Valid Data*
Valid Data Hold Time from RD#
RD# Inactive to RXF#
50
-
-
ns
ns
ns
ns
ns
ns
50 + T6
20
0
50
-
0
25
-
RXF# Inactive After RD# Cycle
80
Table 3.9 FIFO Read Cycle Timing
* Load = 30pF
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