Document Reference No.: FT_000164
V2DIP2-32 VNCL2-32Q Development Module Datasheet Version 1.01
Clearance No.: FTDI# 151
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3.6 Parallel FIFO Interface - Asynchronous Mode
The Parallel FIFO Asynchronous mode is functionally the same as the Parallel FIFO Interface present in
VDIP1 has an eight bit data bus, individual read and write strobes and two hardware flow control signals.
3.6.1 Signal Description - Parallel FIFO Interface
The Parallel FIFO Interface signals can be programmed to a choice of available I/O pins. Table 3.6
shows the Parallel FIFO Interface signals and the pins that they can be mapped.
Available Pins
Name
Type
Description
I/O
I/O
FIFO data bus Bit 0
FIFO data bus Bit 1
J2-10, J1-6, J1-11
fifo_data[0]
fifo_data[1]
J2-9, J1-8, J1-12
I/O
I/O
I/O
I/O
I/O
J2-8, J1-9, J2-12
J2-6, J1-10, J2-11
J2-10, J1-6, J1-11
J2-9, J1-8, J1-12
fifo_data[2]
fifo_data[3]
fifo_data[4]
fifo_data[5]
FIFO data bus Bit 2
FIFO data bus Bit 3
FIFO data bus Bit 4
FIFO data bus Bit 5
FIFO data bus Bit 6
J2-8, J1-9, J2-12
J2-6, J1-10, J2-11
fifo_data[6]
fifo_data[7]
I/O
FIFO data bus Bit 7
When high, do not read data from
the FIFO. When low, there is data
available in the FIFO which can be
read by strobing RD# low, then high.
J2-10, J1-6, J1-11
J2-9, J1-8, J1-12
fifo_rxf#
fifo_txe#
Output
Output
When high, do not write data into the
FIFO. When low, data can be written
into the FIFO by strobing WR high,
then low.
Enables the current FIFO data byte
on D0...D7 when low. Fetches the
next FIFO data byte (if available)
from the receive FIFO buffer when
RD# goes from high to low
J2-8, J1-9, J2-12
J2-6, J1-10, J2-11
fifo_rd#
fifo_wr#
Input
Input
Writes the data byte on the D0...D7
pins into the transmit FIFO buffer
when WR goes from high to low.
Table 3.6 - Data and Control Bus Signal Mode Options – Parallel FIFO Interface
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