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V2DIP1-64 参数 Datasheet PDF下载

V2DIP1-64图片预览
型号: V2DIP1-64
PDF下载: 下载PDF文件 查看货源
内容描述: 设计,让使用VNC2-64Q IC设计快速发展 [Designed to allow rapid development of designs using the VNC2-64Q IC]
分类和应用:
文件页数/大小: 26 页 / 998 K
品牌: FTDI [ FUTURE TECHNOLOGY DEVICES INTERNATIONAL LTD. ]
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Document Reference No.: FT_000165  
V2DIP1-64 VNCL2-64Q Development Module Datasheet Version 1.01  
Clearance No.: FTDI# 154  
3.4 UART Interface  
When the data and control buses are configured in UART mode, the interface implements a standard  
asynchronous serial UART port with flow control. The UART can support baud rates from 300baud to  
3Mbaud. Further details on the UART interface are available on the the Vinculum-II datasheet please  
refer to:- FTDI website  
3.4.1 Signal Description UART Interface  
The UART signals can be programmed to a choice of available I/O pins. Table 3.3 explains the available  
pins for each of the UART signals.  
Available Pins  
Name  
Type  
Description  
J2-14, J1-17, J1-24, J1-29, J2-28, J2-  
23, J1-3, J1-7, J2-8, J2-4  
Transmit asynchronous data  
output  
uart_txd  
uart_rxd  
Output  
Input  
J2-17, J1-14, J1-18, J1-26, J1-30, J2-  
27, J2-22, J1-4, J1-8, J2-7, J2-3  
Receive asynchronous data input  
J2-16, J1-15, J1-20, J1-27, J2-30, J2-  
26, J1-1, J1-5, J1-9, J2-6, J2-2  
uart_rts#  
uart_cts#  
Output  
Input  
Request To Send Control Output  
Clear To Send Control Input  
J2-15, JI-16, J1-21, J1-28, J2-29, J2-24,  
J1-2, J1-6, J2-9, J2-5, J2-1  
J2-14, J1-17, J1-24, J1-29, J2-28, J2-  
23, J1-3, J1-7, J2-8, J2-4  
Data Acknowledge (Data  
Terminal Ready Control) Output  
uart_dtr#  
Output  
J2-17, J1-14, J1-18, J1-26, J1-30, J2-  
27, J2-22, J1-4, J1-8, J2-7, J2-3  
Data Request (Data Set Ready  
Control) Input  
uart_dsr#  
uart_dcd#  
Input  
Input  
J2-16, J1-15, J1-20, J1-27, J2-30, J2-  
26, J1-1, J1-5, J1-9, J2-6, J2-2  
Data Carrier Detect Control Input  
Ring Indicator Control Input. RI#  
low can be used to resume the  
PC USB Host controller from  
suspend.  
J2-15, JI-16, J1-21, J1-28, J2-29, J2-24,  
J1-2, J1-6, J2-9, J2-5, J2-1  
uart_ri#  
Input  
Enable Transmit Data for RS485  
designs. uart_tx_active may be  
used to signal that a transmit  
operation is in progress. The  
uart_tx_active signal will be set  
high one bit-time before data is  
transmitted and return low one  
bit time after the last bit of a  
data frame has been transmitted  
J2-14, J1-17, J1-24, J1-29, J2-28, J2-  
23, J1-3, J1-7, J2-8, J2-4  
uart_tx_active  
Output  
Table 3.3 - Data and Control Bus Signal Mode Options UART  
Copyright © 2010 Future Technology Devices International Limited  
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