Datasheet
Vinculum-II Embedded Dual USB Host Controller IC
Version 1.7
Document No.: FT_000138 Clearance No.: FTDI#143
Figure 6.18 SPI Slave Mode Data Write
6.3.6.4 SPI Master Status Read Transaction in VNC1L legacy mode
The VNC2 has a status byte which determines the state of the Receive and Transmit Buffers. The SPI
master must poll VNC2 and read the status byte.
The Start and Setup sequence is sent to VNC2 by the SPI master, see Figure 6.19. The VNC2 clocks out
its status byte on subsequent rising edge clock cycles from the SPI master. This is followed by a status
bit generated by VNC2 (also on the MISO) which will always be zero (indicating new data).
The meaning of the bits within the status byte sent by VNC2 during a Status Read operation is described
in Table 6.12. The result of the Status Read transaction is only valid during the transaction itself. Data
read and data write transactions must still check the status bit during a Data Read or Data Write cycle
regardless of the result of a Status Read operation.
Bit
0
Description
Description
Receive Buffer Full
RXF#
1
TXE#
Transmit Buffer Empty
2
-
Not used
3
-
Not used
4
RXF IRQEn
Receive Buffer Full Interrupt Enable
Transmit Buffer Empty Interrupt Enable
Not used
5
TXE IRQEn
6
-
-
7
Not used
Table 6.12 SPI Status Read Byte – bit descriptions
Figure 6.19 SPI Slave Mode Status Read
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