Datasheet
Vinculum-II Embedded Dual USB Host Controller IC
Version 1.7
Document No.: FT_000138 Clearance No.: FTDI#143
With reference to Figure 5.3, it can be seen that IOBUS9-11 and IOBUS16-19 were unused. Figure 5.4
expands upon the previous two figures to detail a fully occupied IOBUS, up to and including IOBUS19.
The gaps at IOBUS9-11 have been filed with 3 GPIO pins, the gaps at IOBUS16-19 have been filled with
the second SPI slave and a further 3 IOBUS pins (17-19) have been allocated to 3 GPIO pins. Note that
GPIO pins A0 and A4 are unusedas a sufficient gap wasn't available.
Peripheral Pin
IOBUS Pin
uart_txd
uart_rxd
IOBUS0
IOBUS1
uart_rts#
uart_cts#
uart_dtr#
uart_dsr#
uart_dcd#
uart_ri#
IOBUS2
IOBUS3
IOBUS4
IOBUS5
IOBUS6
IOBUS7
uart_tx_active
IOBUS8
IOBUS9
spi_s0_clk
spi_s0_mosi
spi_s0_miso
spi_s0_ss#
IOBUS10
IOBUS11
IOBUS12
IOBUS13
IOBUS14
IOBUS15
IOBUS16
IOBUS17
IOBUS18
IOBUS19
IOBUS20
IOBUS21
IOBUS22
IOBUS23
IOBUS24
IOBUS25
IOBUS26
IOBUS27
IOBUS28
IOBUS29
IOBUS30
IOBUS31
spi_s1_clk
spi_s1_mosi
spi_s1_miso
spi_s1_ss#
spi_m_clk
spi_m_mosi
spi_m_miso
spi_m_ss_0#
spi_m_ss_1#
gpio[A0]
gpio[A1]
gpio[A2]
gpio[A3]
gpio[A4]
gpio[A5]
gpio[A6]
gpio[A7]
IOBUS43
gpio[E7]
Figure 5.4 IOBUS to UART, SPI slave0 and SPI master third example
28
Copyright © Future Technology Devices International Limited
FTDI [ FUTURE TECHNOLOGY DEVICES INTERNATIONAL LTD. ]
