FT51A Advanced MCU with 8051 Compatible Core IC Datasheet
Version 1.5
Document No.: FT_000877
Clearance No.: FTDI#420
3.2.14 I2C Slave
The FT51A provides an interface between the core and an I2C bus. It can work as a slave receiver or
transmitter depending on the working mode determined by the core. The core incorporates all features
required by the I2C specification. The Slave supports all the transmission modes: Standard, Fast, Fast‐
plus and High Speed. Clock stretching is supported.
3.2.15 SPI Slave
The Serial Peripheral Interface Bus is an industry standard communications interface. Devices
communicate in Master / Slave mode, with the Master initiating the data transfer.
The SPI slave module has four signals – clock, slave select, MOSI (master out – slave in) and MISO
(master in – slave out).
3.2.16 SPI Master
CLK
SS#
External - SPI Slave
SPI Master
MOSI
MISO
Figure 3-2 – SPI Master
The SPI Master interface is used to interface to applications such as SD Cards.
The main purpose of the SPI Master block is to transfer data between an external SPI interface and the
FT51A. It does this under the control of the CPU and DMA engine via the on-chip IO bus.
The SPI master module has seven signals – clock, slave select 0..3, MOSI (master out – slave in) and
MISO (master in – slave out).
The SPI Master protocol by default does not support any form of handshaking and the only available
mode is unmanaged.
The SPI Master clock can operate up to half of the CPU system clock:
CPU running at 48 Mhz would set the SPI maximum clock to 24 Mhz
CPU running at 24 Mhz would set the SPI maximum clock to 12 Mhz
CPU running at 12 Mhz would set the SPI maximum clock to 6 Mhz
3.2.17 Debugger
The purpose of the debugger interface is to provide the Integrated Development Environment (IDE) with
the following capabilities:
MTP Program.
Application debug - application code can have breakpoints, be single stepped and can be halted.
Detailed internal debug - memory read/write access.
The single wire interface has the following features:
Half Duplex Operation
1Mbps speed
1 start bit
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