欢迎访问ic37.com |
会员登录 免费注册
发布采购

FT51AQ-R 参数 Datasheet PDF下载

FT51AQ-R图片预览
型号: FT51AQ-R
PDF下载: 下载PDF文件 查看货源
内容描述: [Supports DMA operation]
分类和应用:
文件页数/大小: 43 页 / 1683 K
品牌: FTDI [ FUTURE TECHNOLOGY DEVICES INTERNATIONAL LTD. ]
 浏览型号FT51AQ-R的Datasheet PDF文件第10页浏览型号FT51AQ-R的Datasheet PDF文件第11页浏览型号FT51AQ-R的Datasheet PDF文件第12页浏览型号FT51AQ-R的Datasheet PDF文件第13页浏览型号FT51AQ-R的Datasheet PDF文件第15页浏览型号FT51AQ-R的Datasheet PDF文件第16页浏览型号FT51AQ-R的Datasheet PDF文件第17页浏览型号FT51AQ-R的Datasheet PDF文件第18页  
FT51A Advanced MCU with 8051 Compatible Core IC Datasheet  
Version 1.5  
Document No.: FT_000877  
Clearance No.: FTDI#420  
3.2.11 USB XCVR  
The USB Transceiver Cell provides the USB 2.0 full-speed physical interface to the USB cable. The output  
drivers provide +3.3V level slew rate control signalling, whilst a differential input receiver and two single  
ended input receivers provide USB data in, Single-Ended-0 (SE0) and USB reset detection conditions  
respectfully. This function also incorporates a 1.5kΩ pull up resistor on the USBUPDP pin.  
3.2.12 IO Multiplexer  
With the addition of the IO multiplexer any function can be configured to any DIO pin, excluding the  
analogue ADC function which is constrained to the AIO pins. All other digital functionality is  
recommended to map to DIO pins. The IO multiplexer allows the designer to select which peripherals are  
connected to which IO pins. In order to assign a signal to a particular pin, two register writes are  
required, one to select the signal and the other to select the IO pin. The FT51A Programmer’s Guide  
details the pins and signals which can be connected.  
The selectable peripheral interfaces are only limited by the number of IO pins available. The number of  
IOs available is dependent on the package type.  
Table 3-2 lists the peripherals which can be multiplexed to IO and the typical number of pins required for  
each one. The designer can choose any mix of peripheral configurations as long as they are within the  
specific package IO pin count.  
Number of pins required  
Peripherals  
(typical)  
UART (FTDI)  
UART (8051)  
ADC  
4
2
1-16  
32  
4
8051 Port 0-3  
SPI Master  
SPI Slave  
245 FIFO  
I2C Master  
I2C Slave  
PWM  
4
12  
2
2
1-8  
Table 3-2 Peripheral Pin Requirements  
3.2.13 I2C Master  
The FT51A provides an interface between the core andan I2C bus. It can be programmed to operate with  
arbitration and clock synchronization allowingit to operate in multimaster systems. I2C Master supports  
transmission speeds up to 3.4 Mb/s including Normal, Fast and High Speed modes.  
Copyright © Future Technology Devices International Limited  
14