FT51A Advanced MCU with 8051 Compatible Core IC Datasheet
Version 1.5
Document No.: FT_000877
Clearance No.: FTDI#420
Appendix C – List of IO registers
User should refer to the FT51A Programmer’s Guide for more detail.
Register
Register Name
Description
Address
(0x0)
(0x1)
(0x2)
(0x3)
(0x4)
(0x5)
(0x6)
(0x9)
DEVICE_CONTROL_REGISTER
SYSTEM_CLOCK_DIVIDER
TOP_USB_CONTROL
PERIPHERAL_INT0
PERIPHERAL_IEN0
PERIPHERAL_INT1
PERIPHERAL_IEN1
PIN_CONFIG
Device Control Register
System Clock Divider
USB Top-level Control Register
Peripheral Interrupt Status 0
Peripheral Interrupt Enable 0
Peripheral Interrupt Status 1
Peripheral Interrupt Enable 1
Miscellaneous Pin Configuration
(0xA)
to
(0x19)
(0x1A)
to
DIGITAL_CONTROL_AIO_0
to
DIGITAL_CONTROL_AIO15
DIGITAL_CONTROL_DIO0
to
AIO Pins 0 to 15 Digital Control
DIO Pins 0 to 15 Digital Control
(0x29)
DIGITAL_CONTROL_DIO15
(0x2A)
(0x2B)
(0x2C)
(0x2D)
(0x2E)
(0x34)
(0x36)
(0x37)
(0x38)
(0x39)
(0x40)
(0x41)
(0x42)
(0x43)
(0x44)
(0x48)
(0x4A)
(0x4B)
(0x4C)
(0x4D)
(0x4E)
(0x50)
(0x51)
(0x52)
(0x53)
(0x54)
(0x55)
(0x56)
(0x57)
(0x58)
(0x59)
(0x5A)
(0x5B)
(0x60)
(0x61)
(0x62)
(0x63)
(0x64)
AIO_DIFFERENTIAL_ENABLE
MTP_CONTROL
MTP_PROG_ADDR_L
MTP_PROG_ADDR_U
MTP_PROG_DATA
PIN_PACKAGE_CONFIG
CRC_CONTROL
CRC_RESULT_L
AIO Differential Pin Enable
MTP Memory Control
MTP Program Address Lower Byte
MTP Program Address Upper Byte
MTP Program Data
Device Package Information
CRC Control of MTP Memory
CRC Result Lower Byte
CRC_RESULT_U
SECURITY_LEVEL
IOMUX_CONTROL
CRC Result Upper Byte
Device Security Status Register
IOMUX Control Register
IOMUX_OUTPUT_PIN_SEL
IOMUX_OUTPUT_SIG_SEL
IOMUX_INPUT_SIG_SEL
IOMUX_INPUT_PIN_SEL
SPI_SLAVE_CONTROL
SPI_SLAVE_TX_DATA
SPI_SLAVE_RX_DATA
SPI_SLAVE_IEN
SPI_SLAVE_INT
SPI_SLAVE_SETUP
SPI_MASTER_CONTROL
SPI_MASTER_DATA_TX
SPI_MASTER_DATA_RX
SPI_MASTER_IEN
Select Output Pin Number Register
Select Output Signal Register
Select Input Signal Register
Select Input Pin Number Register
SPI_SLAVE Control Register
SPI Slave Transmit Data
SPI Slave Receive Data
SPI Slave Interrupt Enable
SPI Slave Interrupt Status
SPI Slave Setup
SPI_MASTER Control Register
SPI Master Transmit Data
SPI Master Receive Data
SPI Master Interrupt Enable
SPI Master Interrupt Status
SPI Master Setup
SPI_MASTER_INT
SPI_MASTER_SETUP
SPI_MASTER_CLK_DIV
SPI_MASTER_DATA_DELAY
SPI_MASTER_SS_SETUP
SPI_MASTER_TRANSFER_SIZE_L
SPI_MASTER_TRANSFER_SIZE_U
SPI_MASTER_TRANSFER_PENDING
UART_CONTROL
UART_DMA_CTRL
UART_RX_DATA
UART_TX_DATA
UART_TX_IEN
SPI Master Clock Divider
SPI Master Data Delay
SPI Master Slave Select Setup
SPI Master Transfer Size Lower Byte
SPI Master Transfer Size Upper Byte
SPI Master Transfer Pending
UART Control Register
UART DMA Control
UART Receive Data
UART Transmit Data
UART Tx Interrupt Enable
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