FT51A Advanced MCU with 8051 Compatible Core IC Datasheet
Version 1.5
Document No.: FT_000877
Clearance No.: FTDI#420
1 stop bit
8 data bits
Pull up
3.2.18 245 FIFO
The 245 FIFO interface operating in asynchronous mode has an eight bit data bus, individual read and
write strobes with two hardware flow control signals.
3.2.19 PWM
The Pulse Width Modulation(PWM) block can generate a signal in which parameters such as period and
duty cycle are controlled by the 8051 core. It provides 8 outputs and can generate a core interrupt if set.
The main purpose is to generate PWM signals which can be used to control motors, DC/DC converters,
AC/DC supplies, etc.
3.2.20 Digital IO pins
Up to 16 General Purpose digital IO pins are available depending on the package type.
3.2.21 Analogue IO pins
Up to 16 AIO pins are available depending on the package type. The pin can function in either analogue
or digital mode, but not both modes at the same time.
When in analogue mode all 16 AIO pins can be configured to the ADC mode.
AIO_mode_1
0
AIO_mode_0
0
Configuration
Analogue off. If the pin is configured for digital mode, it can be
controlled similar to digital IO pins.
0
1
1
0
Reserved.
ADC mode. Analogue input signal for the internal ADC
convertor.
1
1
Reserved.
Table 3-3 – AIO Modes
To configure these modes, specific registers of the AIOs must be configured. On top of these modes sits a
global mode which allows multiple control of AIO pins. All 16 pins can be configured depending on the
package type.
3.2.22 ADC
The ADC block can convert the analogue input signal to a digital value and store the value in the
registers. The ADC block can be configured to work in single-ended mode and differential mode. In
single-ended mode, an input signal fromany of the AIO pins can be the input to the ADC block, with the
reference voltage connectedto VOUT3V3. In differential mode, two AIO pins are used together to form a
pair of differential inputs. The voltage difference between these two pins will be converted to digital
values.
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