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FT4232H-56Q 参数 Datasheet PDF下载

FT4232H-56Q图片预览
型号: FT4232H-56Q
PDF下载: 下载PDF文件 查看货源
内容描述: [Quad High Speed USB to Multipurpose UART/MPSSE IC]
分类和应用:
文件页数/大小: 55 页 / 1663 K
品牌: FTDI [ FUTURE TECHNOLOGY DEVICES INTERNATIONAL LTD. ]
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FT4232H QUAD HIGH SPEED USB TO MULTIPURPOSE UART/MPSSE IC  
Datasheet  
Version 2.4  
Document No.: FT_000060 Clearance No.: FTDI#78  
RS485 is a multi-drop network i.e. many devices can communicate with each other over a single two  
wire cable connection. The RS485 cable requires to be terminated at each end of the cable. Links are  
provided to allow the cable to be terminated if the device is physically positioned at either end of the cable.  
In this example the data transmitted by the FT4232H is also received by the device that is transmitting.  
This is a common feature of RS485 and requires the application software to remove the transmitted data  
from the received data stream. With the FT4232H it is possible to do this entirely in hardware simply  
modify the schematic so that RXD of the FT4232H is the logical OR of the level converter device receiver  
output with TXDEN using an HC32 or similar logic gate.  
4.4 MPSSE Interface Mode Description  
MPSSE Mode is designed to allow the FT4232H to interface efficiently with synchronous serial protocols  
such as JTAG, I2C and SPI Bus. It can also be used to program SRAM based FPGA’s over USB. The MPSSE  
interface is designed to be flexible so that it can be configured to allow any synchronous serial protocol  
(industry standard or proprietary) to be implemented using the FT4232H. MPSSE is only available on  
channel A and channel B.  
MPSSE is fully configurable, and is programmed by sending commands down the data stream. These can  
be sent individually or more efficiently in packets. MPSSE is capable of a maximum sustained data rate of  
30 Mbits/s.  
When a channel is configured in MPSSE mode, the IO timing and signals used are shown in Figure 4.4 and  
Table 4.1. These show timings for CLKOUT=30MHz. CLKOUT can be divided internally to be provide a  
slower clock.  
Figure 4.4 MPSSE Signal Waveforms  
Copyright © Future Technology Devices International Limited  
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