DS_FT311D USB ANDROID HOST IC Datasheet
Version 1.2
Document No.: FT_000660 Clearance No.: FTDI# 305
Mode CPOL CPHA
0
1
2
3
0
0
1
1
0
1
0
1
Table 5.3 - Clock Phase/Polarity Modes
Figure 5-5 - SPI CPOL CPHA Function
5.5.2 Serial Peripheral Interface – Slave
CLK
SS#
FT311 - SPI Slave
External - SPI Master
MOSI
MISO
Figure 5-6 SPI Slave block diagram
FT311D has an SPI Slave module that uses four wire interfaces: MOSI, MISO, CLK and SS#. An SPI
transfer can only be initiated by the SPI Master and begins with the slave select signal being asserted.
This is followed by a data byte being clocked out with the master supplying CLK. The master always
supplies the first byte, which is called a command byte. After this the desired number of data bytes are
transferred before the transaction is terminated by the master de-asserting slave select. An SPI Master is
able to abort a transfer at any time by de-asserting its SS# output. This will cause the Slave to end its
current transfer and return to idle state.
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