DS_FT311D USB ANDROID HOST IC Datasheet
Version 1.2
Document No.: FT_000660 Clearance No.: FTDI# 305
2. If the UART device has an enable pin(active high enable) such as on the GPS module, the
USB_ERROR# can also be used. The USB_ERROR# pin may be inverted with an NPN BJT then connected
to the enable pin of the GPS module.
Figure 5-4 Inverting Gate Control signal to enable GPS module(active high enable)
5.3 Pulse Width Modulation
FT311D provides 4 Pulse Width Modulation (PWM) outputs. These can be used to generate PWM signals
which can be used to control motors, DC/DC converters, AC/DC supplies, etc. Further information is
available in an Application Note AN_140 - Vinculum-II PWM Example.
The features of the PWM module are as follows:
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-
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4 PWM outputs
Variable frequency
Variable duty cycle
5.4 I2C
I2C (Inter Integrated Circuit) is a multi-master serial bus invented by Philips. I2C uses two bi-directional
open-drain wires called serial data (SDA) and serial clock (SCL). Common I²C bus speeds are the 100
kbit/s standard mode (SM), 400 kbit/s fast mode (FM), 1 Mbit/s Fast mode plus (FM+), and 3.4 Mbit/s
High Speed mode (HS)
An I2C bus node can operate either as a master or a slave:
.
.
Master node
Slave node
– issues the clock and addresses slaves
– receives the clock line and address.
FT311D provides an I2C master interface for connection to other I2C Slave interfaces up to 125kbit/s.
The master is initially in master transmit mode by sending a start bit followed by the 7-bit address of the
slave it wishes to communicate with, which is finally followed by a single bit representing whether to
write(0) to, or read(1) from the slave.
If the slave exists on the bus then it will respond with an ACK bit (active low for acknowledged) for that
address. The master then continues in either transmit or receive mode (according to the read/write bit it
sent), and the slave continues in its complementary mode (receive or transmit, respectively).
The address and the data bytes are sent most significant bit first. The start bit is indicated by a high-to-
low transition of SDA with SCL high; the stop bit is indicated by a low-to-high transition of SDA with SCL
high.
If the master has to write to the slave then it repeatedly sends a byte with the slave sending an ACK bit.
(In this situation, the master is in master transmit mode and the slave is in slave receive mode.)
If the master has to read from the slave then it repeatedly receives a byte from the slave, the master
sending an ACK bit after every byte but the last one. (In this situation, the master is in master receive
mode and the slave is in slave transmit mode.)
The master then ends transmission with a stop bit, or it may send another START bit if it wishes to retain
control of the bus for another transfer (a "combined message").
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