欢迎访问ic37.com |
会员登录 免费注册
发布采购

FT245RL-2000 参数 Datasheet PDF下载

FT245RL-2000图片预览
型号: FT245RL-2000
PDF下载: 下载PDF文件 查看货源
内容描述: USB FIFO IC - 单芯片USB转并行FIFO双向数据传输接口 [USB FIFO IC - Single chip USB to parallel FIFO bidirectional data transfer interface]
分类和应用: 先进先出芯片数据传输
文件页数/大小: 37 页 / 761 K
品牌: FTDI [ FUTURE TECHNOLOGY DEVICES INTERNATIONAL LTD. ]
 浏览型号FT245RL-2000的Datasheet PDF文件第12页浏览型号FT245RL-2000的Datasheet PDF文件第13页浏览型号FT245RL-2000的Datasheet PDF文件第14页浏览型号FT245RL-2000的Datasheet PDF文件第15页浏览型号FT245RL-2000的Datasheet PDF文件第17页浏览型号FT245RL-2000的Datasheet PDF文件第18页浏览型号FT245RL-2000的Datasheet PDF文件第19页浏览型号FT245RL-2000的Datasheet PDF文件第20页  
Document No.: FT_000052  
FT245R USB FIFO IC Datasheet Version 2.10  
Clearance No.: FTDI# 39  
4.2 Functional Block Descriptions  
The following paragraphs detail each function within the FT245R. Please refer to the block  
diagram shown in Figure 2.1.  
Internal EEPROM. The internal EEPROM in the FT245R is used to store USB Vendor ID (VID), Product ID  
(PID), device serial number, product description string and various other USB configuration descriptors.  
The FT245R is supplied with the internal EEPROM pre-programmed as described in Section 9. A user area  
of the internal EEPROM is available to system designers to allow storing additional data. The internal  
EEPROM descriptors can be programmed in circuit, over USB without any additional voltage requirement.  
It can be programmed using the FTDI utility software called MPROG and FT_PROG, which can be  
downloaded from FTDI Utilities on the FTDI website (www.ftdichip.com).  
+3.3V LDO Regulator. The +3.3V LDO regulator generates the +3.3V reference voltage for driving the  
USB transceiver cell output buffers. It requires an external decoupling capacitor to be attached to the  
3V3OUT regulator output pin. It also provides +3.3V power to the 1.5kΩ internal pull up resistor on  
USBDP. The main function of the LDO is to power the USB Transceiver and the Reset Generator Cells  
rather than to power external logic. However, it can be used to supply external circuitry requiring a  
+3.3V nominal supply with a maximum current of 50mA.  
USB Transceiver. The USB Transceiver Cell provides the USB 1.1 / USB 2.0 full-speed physical interface  
to the USB cable. The output drivers provide +3.3V level slew rate control signalling, whilst a differential  
input receiver and two single ended input receivers provide USB data in, Single-Ended-0 (SE0) and USB  
reset detection conditions respectfully. This function also incorporates the internal USB series termination  
resistors on the USB data lines and a 1.5kΩ pull up resistor on USBDP.  
USB DPLL. The USB DPLL cell locks on to the incoming NRZI USB data and generates recovered clock  
and data signals for the Serial Interface Engine (SIE) block.  
Internal 12MHz Oscillator. The Internal 12MHz Oscillator cell generates a 12MHz reference clock. This  
provides an input to the x4 Clock Multiplier function. The 12MHz Oscillator is also used as the reference  
clock for the SIE, USB Protocol Engine and FIFO controller blocks.  
Clock Multiplier / Divider. The Clock Multiplier / Divider takes the 12MHz input from the Internal  
Oscillator function and generates the 48MHz. The 48Mz clock reference is used by the USB DPLL and the  
Baud Rate Generator blocks.  
Serial Interface Engine (SIE). The Serial Interface Engine (SIE) block performs the parallel to serial  
and serial to parallel conversion of the USB data. In accordance with the USB 2.0 specification, it  
performs bit stuffing/un-stuffing and CRC5/CRC16 generation. It also checks the CRC on the USB data  
stream.  
USB Protocol Engine. The USB Protocol Engine manages the data stream from the device USB control  
endpoint. It handles the low level USB protocol requests generated by the USB host controller and the  
commands for controlling the functional parameters of the FIFO in accordance with the USB 2.0  
specification Section 10.  
FIFO RX Buffer (128 bytes). Data sent from the USB host controller to the FIFO via the USB data OUT  
endpoint is stored in the FIFO RX (receive) buffer and is removed from the buffer by reading the contents  
of the FIFO using the RD# pin. (Rx relative to the USB interface).  
FIFO TX Buffer (256 bytes). Data written into the FIFO using the WR pin is stored in the FIFO TX  
(transmit) Buffer. The USB host controller removes data from the FIFO TX Buffer by sending a USB  
request for data from the device data IN endpoint. (Tx relative to the USB interface).  
FIFO Controller with Programmable High Drive. The FIFO Controller handles the transfer of data  
between the FIFO RX, the FIFO TX buffers and the external FIFO interface pins (D0 - D7).  
Additionally, the FIFO signals have a configurable high drive strength capability which is configurable in  
the EEPROM.  
RESET Generator. The integrated Reset Generator Cell provides a reliable power-on reset to the device  
internal circuitry at power up. The RESET# input pin allows an external device to reset the FT245R.  
RESET# can be tied to VCC or left unconnected if not being used.  
Copyright © 2010 Future Technology Devices International Limited  
16