FT245BM USB FIFO ( USB - Parallel ) I.C.
•
Programmable FIFO TX Buffer Timeout
In the previous device, the TX buffer timeout
used to flush remaining data from the TX buffer
was fixed at 16ms timeout. This timeout is now
programmable over USB in 1ms increments
from 1ms to 255ms, thus allowing the device to
be better optimised for protocols requiring faster
response times from short data packets.
based option makes the device pull gently down
its FIFO interface lines when the power is shut
off (PWREN# is High). In this mode, any residual
voltage on external circuitry is bled to GND when
power is removed thus ensuring that external
circuitry controlled by PWREN# resets reliably
when power is restored. PWREN# can also be
used by external circuitry to determine when USB
is in suspend mode (PWREN# goes high).
•
Relaxed VCC Decoupling
The 2nd generation devices now incorporate a level
of on-chip VCC decoupling. Though this does
not eliminate the need for external decoupling
capacitors, it significantly improves the ease of
PCB design requirements to meet FCC, CE and
other EMI related specifications.
•
Send Immediate / WakeUp (SI / WU) signal
The new Send Immediate / WakeUp signal
combines two functions on a single pin. If USB is
in suspend mode (and remote wakeup is enabled
in the EEPROM), strobing this pin low will cause
the device to request a resume from suspend
(WakeUp) on the USB Bus. Normally, this can
be used to wake up the Host PC. During normal
operation, if this pin is strobed low any data in the
device RX buffer will be sent out over USB on the
next Bulk-IN request from the drivers regardless of
the packet size. This can be used to optimise USB
transfer speed for some applications.
•
Bit Bang Mode
The 2nd generation device has a new option
referred to as “Bit Bang” mode. In Bit Bang mode,
the eight FIFO data lines can be switched between
FIFO interface mode and an 8-bit Parallel IO
port. Data packets can be sent to the device and
they will be sequentially sent to the interface at
a rate controlled by an internal timer (equivalent
to the prescaler of the FT232BM device). As well
as allowing the device to be used stand-alone
as a general purpose IO controller for example
controlling lights, relays and switches, some other
interesting possibilities exist. For instance, it may
be possible to connect the device to an SRAM
configurable FPGA as supplied by vendors such as
Altera and Xilinx. The FPGA device would normally
be un-configured (i.e. have no defined function) at
power-up. Application software on the PC could
use Bit Bang Mode to download configuration
data to the FPGA which would define its hardware
function, then after the FPGA device is configured
the FT245BM can switch back into FIFO interface
mode to allow the programmed FPGA device
to communicate with the PC over USB. This
•
Lower Suspend Current
Integration of RCCLK within the device and internal
design improvements reduce the suspend current
of the FT245BM to under 100uA typical (excluding
the 1.5K pull-up on USBDP) in USB suspend
mode. This allows greater margin for peripherals to
meet the USB Suspend current limit of 500uA.
•
Support for USB Isochronous Transfers
Whilst USB Bulk transfer is usually the best
choice for data transfer, the scheduling time of the
data is not guaranteed. For applications where
scheduling latency takes priority over data integrity
such as transferring audio and low bandwidth
video data, the new device now offers an option of
USB Isochronous transfer via an option bit in the
EEPROM.
DS245B Version 1.7
© Future Technology Devices Intl. Ltd. 2005
Page 3 of 24
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