FT240X USB 8-BIT FIFO IC Datasheet
Version 1.3
Document No.: FT_000626 Clearance No.: FTDI# 259
Pin No.
Name
Type
Description
Active low reset pin. This can be used by an external device to reset the
FT240X. If not required can be left unconnected, or pulled up to VCC.
13
RESET# Input
Active low input. May be used to flush the IC buffer back to the PC (Send
Immediate) or if the PC is in suspend mode it can be used as a Wake Up
signal.
7
SIWU#
Input
Configurable CBUS I/O Pin. Function of this pin is configured in the
device MTP memory. See CBUS Signal Options, Table 3.9.
20
19
CBUS5
CBUS6
I/O
I/O
Configurable CBUS I/O Pin. Function of this pin is configured in the
device MTP memory. See CBUS Signal Options, Table 3.9.
Table 3.7 Miscellaneous Signal Group
Pin No.
Name
D0
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Description
FIFO Data Bus Bit 0
FIFO Data Bus Bit 1
FIFO Data Bus Bit 2
FIFO Data Bus Bit 3
FIFO Data Bus Bit 4
FIFO Data Bus Bit 5
FIFO Data Bus Bit 6
FIFO Data Bus Bit 7
21
1
D1
23
6
D2
D3
22
4
D4
D5
5
D6
2
D7
Enables the current FIFO data byte on D0...D7 when low. Fetched the next FIFO
data byte (if available) from the receive FIFO buffer when RD# goes from high to
low. See Section 3.6 for timing diagram.
8
RD#
WR
Input
Input
Output
Writes the data byte on the D0...D7 pins into the transmit FIFO buffer when WR
goes from high to low. See Section 3.7 for timing diagram.
9
When high, do not write data into the FIFO. When low, data can be written into
the FIFO by strobing WR high, then low. During reset this signal pin is tri-state.
See Section 3.7 for timing diagram.
17
TXE#
When high, do not read data from the FIFO. When low, there is data available in
the FIFO which can be read by strobing RD# low, then high again. During reset
this signal pin is tri-state. See Section 3.6 for timing diagram.
18
RXF#
Output
If the Remote Wakeup option is enabled in the internal MTP memory, during USB
suspend mode (PWREN# = 1) RXF# becomes an input. This can be used to wake
up the USB host from suspend mode by strobing this pin low for a minimum of
20ms which will cause the device to request a resume on the USB bus.
Table 3.8 FIFO Interface Group (see note 2)
Notes:
When used in Input Mode, the input pins are pulled to VCCIO via internal 200kΩ resistors. These
pins can be programmed to gently pull low during USB suspend (PWREN# = “1”) by setting an
option in the internal MTP memory.
Copyright © 2013 Future Technology Devices International Limited
10
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