Document No.: FT_000288
FT232H SINGLE CHANNEL HI-SPEED USB TO MULTIPURPOSE UART/FIFO IC
Datasheet Version 1.3
Clearance No.: FTDI #199
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Function Description
The FT232H USB 2.0 Hi-Speed (480Mb/s) to UART/FIFO is an FTDI‟s 6
th
generation of ICs. It can be
configured in a variety of industry standard serial or parallel interfaces, such as UART, FIFO, JTAG, SPI
(MASTER) or I
2
C modes. In addition to these, the FT232H introduces the FT1248 interface and supports a
CPU-Style FIFO mode, bit-bang and a fast serial interface mode.
4.1
Key Features
USB Hi-Speed to UART/FIFO Interface.
The FT232H provides USB 2.0 Hi-Speed (480Mbits/s) to
flexible and configurable UART/FIFO Interfaces.
Functional Integration.
The FT232H integrates a USB protocol engine which controls the physical
Universal Transceiver Macrocell Interface (UTMI) and handles all aspects of the USB 2.0 Hi-Speed
interface. The FT232H includes an integrated +1.8V/3.3V Low Drop-Out (LDO) regulator. It also includes
1Kbytes Tx and Rx data buffers. The FT232H integrates the entire USB protocol on a chip with no
firmware required.
MPSSE.
Multi- Protocol Synchronous Serial Engines (MPSSE), capable of speeds up to 30 Mbits/s,
provides flexible synchronous interface configurations.
FT1248 interface.
The FT232H supports a new proprietary half-duplex FT1248 interface with a variable
bi-directional data bus interface that can be configured as 1, 2, 4, or 8-bits wide and this enables the
flexibility to expand the size of the data bus to 8 pins. For details regarding 2-bit, 4-bit and 8-bit modes,
please refer to application note AN_167_FT1248_Serial_Parallel Interface Basics available from the FTDI
website.
Data Transfer rate.
The FT232H supports a data transfer rate up to 12 Mbaud when configured as an
RS232/RS422/RS485 UART interface upto 40 Mbytes/second over a synchronous 245 parallel FIFO
interface or up to 8 Mbyte/Sec over a asynchronous 245 FIFO interface.
Latency Timer.
A feature of the driver used as a timeout to transmit short packets of data back to the
PC. The default is 16ms, but it can be altered between 1ms and 255ms.
Bus (ACBUS) functionality, signal inversion and drive strength selection.
There are 11
configurable ACBUS I/O pins. These configurable options are:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
TXDEN
- transmit enable for RS485 designs.
PWREN#
- Power control for high power, bus powered designs.
TXLED#
- for pulsing an LED upon transmission of data.
RXLED#
- for pulsing an LED upon receiving data.
TX&RXLED#
- which will pulse an LED upon transmission OR reception of data.
SLEEP#
- indicates that the device going into USB suspend mode.
CLK30 / CLK15 / CLK7.5 -
30MHz, 15MHz and 7.5MHz clock output signal options.
TriSt-PU
– Input pulled up, not used
DRIVE 1
– Output driving high
DRIVE 0
- Output driving low
I/O mode
– ACBUS BitBang
The ACBUS pins can also be individually configured as GPIO pins, similar to asynchronous bit bang mode.
It is possible to use this mode while the UART interface is being used, thus providing up to 4 general
purpose I/O pins which are available during normal operation.
The ACBUS lines can be configured with any one of these input/output options by setting bits in the
external EEPROM see section 3.4.
Copyright © 2011 Future Technology Devices International Limited
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FTDI [ FUTURE TECHNOLOGY DEVICES INTERNATIONAL LTD. ]
