FT232BL USB UART ( USB - Serial) I.C.
3.0
VCC
Block Diagram (Simplified)
PWRCTL
SLEEP#
PWREN#
Dual Port TX
Buffer
128 bytes
48MHz
Baud Rate
Generator
3V3OUT
3.3 Volt
LDO
Regulator
USBDP
USB
Transceiver
USBDM
Serial Interface
Engine
( SIE )
USB
Protocol Engine
UART
FIFO Controller
UART
TXD
RXD
RTS#
CTS#
DTR#
DSR#
DCD#
RI#
TXDEN
TXLED#
RXLED#
Dual Port RX
Buffer
384 Bytes
USB DPLL
3V3OUT
EEPROM
Interface
EECS
EESK
EEDATA
XTOUT
6MHZ
Oscillator
x8 Clock
Multiplier
48MHz
XTIN
12MHz
RESET#
RESET
GENERATOR
RSTOUT#
TEST
GND
3.1
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Functional Block Descriptions
3.3V LDO Regulator
The 3.3V LDO Regulator generates the 3.3 volt
reference voltage for driving the USB transceiver
cell output buffers. It requires an external
decoupling capacitor to be attached to the 3V3OUT
regulator output pin. It also provides 3.3V power to
the RSTOUT# pin. The main function of this block
is to power the USB Transceiver and the Reset
Generator Cells rather than to power external logic.
However, external circuitry requiring 3.3V nominal
at a current of not greater than 5mA could also
draw its power from the 3V3OUT pin if required.
USB Transceiver
The USB Transceiver Cell provides the USB 1.1 /
USB 2.0 full-speed physical interface to the USB
cable. The output drivers provide 3.3 volt level slew
rate control signalling, whilst a differential receiver
and two single ended receivers provide USB data
in, SEO and USB Reset condition detection.
•
USB DPLL
The USB DPLL cell locks on to the incoming NRZI
USB data and provides separate recovered clock
and data signals to the SIE block.
6MHz Oscillator
The 6MHz Oscillator cell generates a 6MHz
reference clock input to the x8 Clock multiplier from
an external 6MHz crystal or ceramic resonator.
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DS232BL Version 1.8
© Future Technology Devices Intl. Ltd. 2005
Page 5 of 25
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