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FT2232H_10 参数 Datasheet PDF下载

FT2232H_10图片预览
型号: FT2232H_10
PDF下载: 下载PDF文件 查看货源
内容描述: 双高速USB TO多用途UART / FIFO IC [DUAL HIGH SPEED USB TO MULTIPURPOSE UART/FIFO IC]
分类和应用: 先进先出芯片
文件页数/大小: 63 页 / 1469 K
品牌: FTDI [ FUTURE TECHNOLOGY DEVICES INTERNATIONAL LTD. ]
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Document No.: FT_000061  
FT2232H DUAL HIGH SPEED USB TO MULTIPURPOSE UART/FIFO IC  
Datasheet Version 2.09  
Clearance No.: FTDI#77  
3.2 FT2232H Pin Descriptions  
This section describes the operation of the FT2232H pins. Both the LQFP and the QFN packages have the  
same function on each pin. The function of many pins is determined by the configuration of the FT2232H.  
The following table details the function of each pin dependent on the configuration of the interface. Each  
of the functions are described in the following table (Note: The convention used throughout this  
document for active low signals is the signal name followed by a #).  
Pins marked ** default to tri-stated inputs with an internal 75KΩ (approx) pull up resistor to VCCIO.  
FT2232H  
Pin  
Pin functions (depends on configuration)  
ASYNC  
Serial  
(RS232)  
Fast  
Serial  
interface  
CPU  
Style  
FIFO  
245 FIFO  
SYNC  
ASYNC  
Bit-bang  
SYNC  
Bit-bang  
Host Bus  
Emulation  
Pin #  
Pin Name  
245 FIFO  
MPSSE  
Channel A  
16  
17  
18  
19  
21  
22  
23  
24  
26  
27  
28  
29  
30  
32  
33  
34  
ADBUS0  
ADBUS1  
ADBUS2  
ADBUS3  
ADBUS4  
ADBUS5  
ADBUS6  
ADBUS7  
ACBUS0  
ACBUS1  
ACBUS2  
ACBUS3  
ACBUS4  
ACBUS5  
ACBUS6  
ACBUS7  
TXD  
RXD  
D0  
D1  
D0  
D1  
D0  
D1  
D0  
D1  
TCK/SK  
TDI/DO  
TDO/DI  
TMS/CS  
GPIOL0  
GPIOL1  
GPIOL2  
GPIOL3  
GPIOH0  
GPIOH1  
GPIOH2  
GPIOH3  
GPIOH4  
GPIOH5  
GPIOH6  
GPIOH7  
D0  
D1  
AD0  
AD1  
AD2  
AD3  
AD4  
AD5  
AD6  
AD7  
A8  
USES  
CHANNEL  
B
RTS#  
CTS#  
DTR#  
DSR#  
DCD#  
RI#  
D2  
D2  
D2  
D2  
D2  
D3  
D3  
D3  
D3  
D3  
D4  
D4  
D4  
D4  
D4  
D5  
D5  
D5  
D5  
D5  
D6  
D6  
D6  
D6  
D6  
D7  
D7  
D7  
D7  
D7  
TXDEN  
**  
RXF#  
TXE#  
RD#  
WR#  
SIWUA  
CLKOUT  
OE#  
**  
RXF#  
TXE#  
RD#  
WR#  
SIWUA  
**  
**  
**  
CS#  
A0  
WRSTB#  
RDSTB#  
**  
WRSTB#  
RDSTB#  
**  
A9  
**  
RD#  
WR#  
SIWUA  
**  
A10  
A11  
A12  
A13  
A14  
A15  
RXLED#  
TXLED#  
**  
SIWUA  
**  
SIWUA  
**  
**  
**  
**  
**  
**  
**  
**  
**  
**  
**  
Channel B  
D0  
38  
39  
40  
41  
43  
44  
45  
46  
48  
52  
53  
54  
55  
57  
58  
BDBUS0  
BDBUS1  
BDBUS2  
BDBUS3  
BDBUS4  
BDBUS5  
BDBUS6  
BDBUS7  
BCBUS0  
BCBUS1  
BCBUS2  
BCBUS3  
BCBUS4  
BCBUS5  
BCBUS6  
TXD  
RXD  
D0  
D1  
D0  
D1  
TCK/SK  
TDI/DO  
TDO/DI  
TMS/CS  
GPIOL0  
GPIOL1  
GPIOL2  
GPIOL3  
GPIOH0  
GPIOH1  
GPIOH2  
GPIOH3  
GPIOH4  
GPIOH5  
GPIOH6  
FSDI  
FSCLK  
FSDO  
FSCTS  
D0  
D1  
CS#  
ALE  
RD#  
WR#  
IORDY  
CLKOUT  
I/O0  
I/O1  
**  
D1  
RTS#  
CTS#  
DTR#  
DSR#  
DCD#  
RI#  
D2  
D2  
D2  
D2  
D3  
D3  
D3  
D3  
D4  
D4  
D4  
D4  
D5  
D5  
D5  
D5  
D6  
D6  
D6  
D6  
D7  
D7  
D7  
D7  
TXDEN  
**  
RXF#  
TXE#  
RD#  
WR#  
SIWUB  
**  
**  
**  
CS#  
A0  
WRSTB#  
RDSTB#  
**  
WRSTB#  
RDSTB#  
**  
**  
**  
RD#  
WR#  
SIWUB  
**  
**  
RXLED#  
TXLED#  
**  
**  
SIWUB  
**  
SIWUB  
**  
SIWUB  
**  
**  
**  
**  
**  
**  
**  
**  
PWRSAV  
#
PWRSAV  
#
PWRSAV  
#
PWRSAV  
#
PWRSAV  
#
PWRSAV  
#
PWRSAV#  
59  
60  
36  
BCBUS7  
GPIOH7  
PWRSAV#  
PWREN#  
PWREN#  
PWREN#  
PWREN#  
PWREN#  
PWREN#  
PWREN#  
PWREN#  
PWREN#  
PWREN#  
SUSPEND  
#
SUSPEND  
#
SUSPEND  
#
SUSPEND  
#
SUSPEND  
#
SUSPEND  
#
SUSPEND  
#
SUSPEND#  
SUSPEND#  
SUSPEND#  
Configuration memory interface  
63  
EECS  
Copyright © 2010 Future Technology Devices International Limited  
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