Document No.: FT_000061
FT2232H DUAL HIGH SPEED USB TO MULTIPURPOSE UART/FIFO IC
Datasheet Version 2.09
Clearance No.: FTDI#77
Appendix A – List of Figures and Tables
List of Tables
Table 3.1 Power and Ground ..........................................................................................................9
Table 3.2 Common Function pins.................................................................................................. 10
Table 3.3 EEPROM Interface Group ............................................................................................... 10
Table 3.4 Channel A and Channel B RS232 Configured Pin Descriptions............................................. 11
Table 3.5 Channel A FT245 Style Synchronous FIFO Configured Pin Descriptions ................................ 12
Table 3.6 Channel A and Channel B FT245 Style Asynchronous FIFO Configured Pin Descriptions.......... 13
Table 3.7 Channel A and Channel B Synchronous or Asynchronous Bit-Bang Configured Pin
Descriptions............................................................................................................................. 14
Table 3.8 Channel A and Channel B MPSSE Configured Pin Descriptions.................................. 15
Table 3.9 Channel B Fast Serial Interface Configured Pin Descriptions.................................... 16
Table 3.10 Channel A and Channel B CPU-style FIFO Interface Configured Pin Descriptions ... 17
Table 3.11 Channel A and Channel B Host Bus Emulation Interface Configured Pin Descriptions
................................................................................................................................................ 18
Table 4.1 FT245 Synchronous FIFO Interface Signal Timings............................................................ 24
Table 4.2 Asynchronous FIFO Timings (based on standard drive level outputs)...................... 27
Table 4.3 MPSSE Signal Timings................................................................................................... 28
Table 4.4 MCU Host Bus Emulation Mode Signal Timings – write cycle............................................... 31
Table 4.5 MCU Host Bus Emulation Mode Signal Timings– read cycle................................................. 32
Table 4.6 Fast Opto-Isolated Serial Interface Signal Timings ............................................................ 34
Table 4.7 CPU-Style FIFO Interface Operation Select .............................................................. 37
Table 4.8 CPU-Style FIFO Interface Operation Read Status Description .................................. 37
Table 4.9 CPU-Style FIFO Interface Operation Signal Timing................................................... 38
Table 4.10 Synchronous Bit-Bang Mode Timing Interface Example Timings........................................ 40
Table 4.11 Configuration Using EEPROM and Application Software ......................................... 43
Table 5.1 Absolute Maximum Ratings ............................................................................................ 44
Table 5.2 Operating Voltage and Current (except PHY).................................................................... 45
Table 5.3 I/O Pin Characteristics VCCIO = +3.3V (except USB PHY pins)........................................... 46
Table 5.4 PHY Operating Voltage and Current................................................................................. 47
Table 5.5 PHY I/O Pin Characteristics ............................................................................................ 47
Table 5.5 ESD Tolerance.............................................................................................................. 47
Table 6.1 OSCI Input characteristics ............................................................................................. 52
Table 8.1 64 pin LQFP Package Details – dimensions (in mm)........................................................... 57
Table 8.2 Reflow Profile Parameter Values ..................................................................................... 59
Table 8.3 Package Reflow Peak Temperature.................................................................................. 59
List of Figures
Figure 2.1 FT2232H Block Diagram .................................................................................................4
Figure 3.1 FT2232H Schematic Symbol............................................................................................7
Figure 4.1 RS232 Configuration.................................................................................................... 21
Figure 4.2 Dual RS422 Configuration............................................................................................. 22
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