Document No.: FT_000061
FT2232H DUAL HIGH SPEED USB TO MULTIPURPOSE UART/FIFO IC
Version 2.21
Clearance No.: FTDI#77
4.9 CPU-style FIFO Interface Mode Description
CPU-style FIFO interface mode is designed to allow a CPU to interface to USB via the FT2232H. This mode
is enabled in the external EEPROM. The interface is achieved using a chip select bit (CS#) and address bit
(A0). When either Channel A or Channel B are in CPU-style Interface mode the IO signal lines are
configured as given in Table 3.10.
This mode uses a combination of CS# and A0 to determine the operation to be carried out. The following
truth-table, Table 4.7, gives the decode values for particular operations.
CS#
A0
X
RD#
WR#
1
0
0
X
X
0
Read Data Pipe
Read Status
Write Data Pipe
Send Immediate
1
Table 4.7 CPU-Style FIFO Interface Operation Select
The Status read is shown in Table 4.8
Data Bit
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
Data
1
Status
Data available (=RXF)
1
Space available (=TXE)
1
Suspend
1
Configured
X
X
X
X
X
X
X
X
Table 4.8 CPU-Style FIFO Interface Operation Read Status Description
Note that bits 7 to 4 can be arbitrary values and that X= not used.
The timing of reading and writing in this mode is shown in Figure 4.17 and Table 4.9.
A0
CS#
WR#
Valid
Valid
t3
t1
t4
t6
RD#
D7..0
Valid
Valid
t2
t5
t7
Figure 4.17 CPU-Style FIFO Interface Operation Signal Waveforms.
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