FT232BQ USB UART ( USB - Serial) I.C.
•
Programmable Receive Buffer Timeout
to the device and they will be sequentially sent to
the interface at a rate controlled by the prescaler
setting. As well as allowing the device to be used
stand-alone as a general purpose IO controller for
example controlling lights, relays and switches,
some other interesting possibilities exist. For
instance, it may be possible to connect the device
to an SRAM configurable FPGA as supplied by
vendors such as Altera and Xilinx. The FPGA
device would normally be un-configured (i.e. have
no defined function) at power-up. Application
software on the PC could use Bit Bang Mode to
download configuration data to the FPGA which
would define its hardware function, then after the
FPGA device is configured the FT232BQ can
switch back into UART interface mode to allow
the programmed FPGA device to communicate
with the PC over USB. This approach allows a
customer to create a “generic” USB peripheral
who’s hardware function can be defined under
control of the application software. The FPGA
based hardware can be easily upgraded or
In the previous device, the receive buffer timeout
used to flush remaining data from the receive
buffer was fixed at 16ms timeout. This timeout is
now programmable over USB in 1ms increments
from 1ms to 255ms, thus allowing the device to
be better optimised for protocols requiring faster
response times from short data packets.
•
TXDEN Timing fix
TXDEN timing has now been fixed to remove the
external delay that was previously required for
RS485 applications at high baud rates. TXDEN
now works correctly during a transmit send-break
condition.
•
Relaxed VCC Decoupling
The 2nd generation devices now incorporate a level
of on-chip VCC decoupling. Though this does
not eliminate the need for external decoupling
capacitors, it significantly improves the ease of
PCB design requirements to meet FCC, CE and
other EMI related specifications.
totally changed simply by changing the FPGA
configuration data file. Application notes, software
and development modules for this application area
will be available from FTDI and other 3rd parties.
•
Improved PreScaler Granularity
The previous version of the Prescaler supported
division by (n + 0), (n + 0.125), (n + 0.25) and
(n + 0.5) where n is an integer between 2 and
16,384 (214). To this we have added (n + 0.375),
(n + 0.625), (n + 0.75) and (n+ 0.875) which can
be used to improve the accuracy of some baud
rates and generate new baud rates which were
previously impossible (especially with higher baud
rates).
•
PreScaler Divide By 1 Fix
The previous device had a problem when the
integer part of the divisor was set to 1. In the 2nd
generation device setting the prescaler value to 1
gives a baud rate of 2 million baud and setting it
to zero gives a baud rate of 3 million baud. Non-
integer division is not supported with divisor values
of 0 and 1.
•
Bit Bang Mode
The 2nd generation device has a new option
referred to as “Bit Bang” mode. In Bit Bang mode,
the eight UART interface control lines can be
switched between UART interface mode and an
8-bit Parallel IO port. Data packets can be sent
DS232BQ Version 1.8
© Future Technology Devices Intl. Ltd. 2005
Page 3 of 25
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