854 Series
8-Bit Programmable Filters
Digital Tuning Characteristics
The digital tuning interface circuits are two 4042 quad CMOS
latches which accept the following CMOS-compatible inputs:
eight tuning bits (D
0
- D
7
), a latch strobe bit (C), and a transition
polarity bit (P).
Filter tuning follows the tuning equation given below:
f
c
= ( f
max
/256 ) [ 1 + D
7
x 2
7
+ D
6
x 2
6
+ D
5
x 2
5
+ D
4
x 2
4
+ D
3
x 2
3
+ D
2
x 2
2
+ D
1
x 2
1
+ D
0
x 2
0
]
where D
1
- D
7
= "0" or "1", and
f
max
= Maximum tuning frequency;
f
c
= corner frequency;
Minimum tunable frequency = f
max
/256 (D
0
thru D
7
= 0);
Minimum frequency step (Resolution) = f
max
/256
Pin-Out Key
IN
OUT
GND
"P"
"C"
+Vs
-Vs
Os
Analog Input Signal
Analog Output Signal
Power and Signal Return
Transition Polarity Bit
Tuning Strobe Bit
Supply Voltage, Positive
Supply Voltage, Negative
Optional Offset Adjustment
D
7
Tuning
D
6
Tuning
D
5
Tuning
D
4
Tuning
D
3
Tuning
D
2
Tuning
D
1
Tuning
D
0
Tuning
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
7 (MSB)
6
5
4
3
2
1
0 (LSB)
Digital Tuning &
Control Characteristics
OUT +Vs -Vs
D
7
D
6
D
5
D
4
GND
D
3
D
2
D
1
D
0
IN Os
Data Control Specifications
Data Control Lines
Functions
Data Control Modes
Mode 1
Mode 2
Input Data Levels
Latch Strobe (C)
Transition Polarity (P)
P = 0; C = 0
P = 0; C = 0›
P = 1; C = 1
P = 1; C = 1fl
(CMOS Logic)
0 Vdc min.
11 Vdc min.
-1
mA
max.
+1
mA
max.
7.5 pF max.
0
25 nS
50 nS
80 nS min.
Frequency Select Bits
Logic "1" = +Vs
Logic "0" = Gnd
(Binary-Coded)
LSB (least significant bit)
MSB (most significant bit)
256 : 1, Binary Weighted
0
0
0
0
1
0
0
0
0
1
1
0
0
0
1
1
1
0
0
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
4 Vdc max.
15 Vdc max.
frequency follows input codes
frequency latched on rising edge
frequency follows input codes
frequency latched on falling edge
Bottom View
---
2
5
D
5
0
0
0
---
2
4
D
4
0
0
0
---
2
3
D
3
0
0
0
---
2
2
D
2
0
0
0
---
2
1
D
1
0
0
1
P C
MSB
2
7
D
7
0
0
0
---
2
6
D
6
0
0
0
LSB
2
0
D
0
0
1
1
Bit
Weight
fc
Corner
Frequency
Input Voltage (Vs = 15 Vdc)
Low Level In
High Level In
Input Current
High Level In
Low Level In
Input Capacitance
Latch Response
1
Data Set Up Time
2
Data Hold Time
Strobe Pulse Width
Input Data Format
Positive Logic
Bit Weighting
D
0
D
7
Frequency Range
- 10
-5
mA
typ.
+10
-5
mA
typ
.
5 pF typ
f
max
/256
f
max
/128
f
max
/64
f
max
/32
f
max
/16
f
max
/8
f
max
/4
f
max
/2
fmax
Notes:
1. Frequency data must be present before occurrence of strobe edge.
2. Frequency data must be present after occurrence of strobe edge.
2
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