428 Series
Digital Tuning &
Control Characteristics
4-Bit Programmable Filters
Digital Tuning Characteristics
Pin-Out Key
The digital tuning interface circuits are a parallel set of CMOS
switches which accept CMOS compatible inputs for the four
tuning bits (D0 - D3).
IN
Analog Input Signal
D3 Tuning Bit 3 (MSB)
D2 Tuning Bit 2
OUT Analog Output Signal
GND Power and Signal Return D1 Tuning Bit 1
+Vs Supply Voltage, Positive D0 Tuning Bit 0 (LSB)
-Vs Supply Voltage, Negative +5V Logic Power
Binary Tuning Range
MSB
---
---
LSB
Bit
Weight
23
D3
22
D2
21
D1
20
D0
fc - corner
frequency
Os
Offset Adjustment
0
0
0
0
1
0
0
0
1
1
0
0
1
1
1
0
1
1
1
1
fmax/16
fmax/8
fmax/4
fmax/2
fmax
0.80"
0.70"
OUT
Os
+Vs
GND
IN
-Vs
Bottom View
Binary Tuning Equation:
fc = (fmax /16) [1+ D3 x 23 + D2 x 22 + D1 x 21 + D0 x 20]
where D1 - D3 = “0” or “1”, and
D1
+5V
D2
D0
D3
0.10"
0.00"
fmax = Maximum tuning frequency
fc = Corner frequency;
Minimum tunable frequency = f
max /16 (D0 thru D3 = 0);
Minimum frequency step (Resolution) = fmax /16
Data Input Specifications
Input Data Levels
Discrete Frequencies
F
D0
0
D1
0
D2
0
D3
0
0
0
0
(+5Vdc CMOS Logic)
FB
F1
F2
F3
F4
1
1
0
1
0
0
Input Voltage (Vs=15 Vdc)
Low Level In
High Level In
0 Vdc min.
3.5 Vdc min.
0.5 Vdc max.
5.0 Vdc max.
1
1
1
1
1
1
1
Input Current
High Level In
Low Level In
Discrete Tuning Equation:
fc = FB + D0[f0] + D1[f1] + D2[f2] + D3[f3]
f0, f1, f2, f3 are the incremental frequency shifts for the data
bits D0, D1, D2 and D3. They are selected to realize the five
-0.4mAtyp.
+0.4mAtyp.
-2.0mAmax.
+2.0m max.
A
customer specified programming frequencies F
programming codes produce valid fc’s between F
F
.
4
Other
.
B ->
Input Capacitance
20 pF typ.
30 pF max.
B and F4
Input Data Format
Positive Logic
Frequency Select Bits
Logic “1” = (+5Vdc)
Logic “0” = Gnd
Bit Weight
(Binary-Coded)
D0
LSB (least significant bit)
D3
MSB (most significant bit)
Frequency Range16:1 Binary Weighted
2
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