CPM Electrical Characteristics
Table 21. SI Timing (continued)
Characteristic
All Frequencies
Num
Unit
Min
Max
75
76
77
78
L1RSYNC, L1TSYNC rise/fall time
L1RXD valid to L1CLK edge (L1RXD setup time)
—
15.00
—
ns
ns
17.00
13.00
10.00
10.00
10.00
10.00
10.00
0.00
L1CLK edge to L1RXD invalid (L1RXD hold time)
—
ns
4
L1CLK edge to L1ST(1–4) valid
45.00
45.00
45.00
55.00
55.00
42.00
ns
78A L1SYNC valid to L1ST(1–4) valid
ns
79
80
L1CLK edge to L1ST(1–4) invalid
L1CLK edge to L1TXD valid
ns
ns
80A L1TSYNC valid to L1TXD valid 4
ns
81
82
L1CLK edge to L1TXD high impedance
L1RCLK, L1TCLK frequency (DSC =1)
ns
—
16.00 or
SYNCCLK
/2
MHz
83
L1RCLK, L1TCLK width low (DSC =1)
P + 10
P + 10
—
—
—
ns
ns
83a L1RCLK, L1TCLK width high (DSC = 1)3
84
85
86
87
88
L1CLK edge to L1CLKO valid (DSC = 1)
L1RQ valid before falling edge of L1TSYNC4
L1GR setup time2
30.00
—
ns
1.00
42.00
42.00
—
L1TCLK
ns
—
L1GR hold time
—
ns
L1CLK edge to L1SYNC valid (FSD = 00) CNT = 0000, BYT = 0,
DSC = 0)
0.00
ns
1 The ratio SyncCLK/L1RCLK must be greater than 2.5/1.
2 These specs are valid for IDL mode only.
3 Where P = 1/CLKOUT. Thus for a 25-MHz CLKO1 rate, P = 40 ns.
4 These strobes and TxD on the first bit of the frame become valid after L1CLK edge or L1SYNC, whichever comes later.
MPC885/MPC880 Hardware Specifications, Rev. 3
53
Freescale Semiconductor
FREESCALE [ Freescale ]
