System Design Information
Figure 62 shows the PLL power supply filter circuits.
10 Ω
V
AV
DD
DD
2.2 µF
2.2 µF
Low ESL Surface Mount Capacitors
GND
Figure 62. PLL Power Supply Filter Circuit
NOTE
It is recommended to have the minimum number of vias in the AV trace
DD
for board layout. For example, zero vias might be possible if the AV filter
DD
is placed on the component side. One via might be possible if it is placed on
the opposite of the component side. Additionally, all traces for AV and
DD
the filter components should be low impedance, 10 to 15 mils wide and
short. This includes traces going to GND and the supply rails they are
filtering.
The AV _SRDSn signal provides power for the analog portions of the SerDesn PLL. To ensure stability
DD
of the internal clock, the power supplied to the PLL is filtered using a circuit similar to the one shown in
following figure. For maximum effectiveness, the filter circuit is placed as closely as possible to the
AV _SRDSn ball to ensure it filters out as much noise as possible. The ground connection should be near
DD
the AV _SRDSn ball. The 0.003-µF capacitor is closest to the ball, followed by the two 2.2 µF
DD
capacitors, and finally the 1 Ω resistor to the board supply plane. The capacitors are connected from
AV _SRDSn to the ground plane. Use ceramic chip capacitors with the highest possible self-resonant
DD
frequency. All traces should be kept short, wide and direct.
1.0 Ω
SV
AV _SRDSn
DD_SRDSn
DD
1
1
0.003 µF
2.2 µF
2.2 µF
GND
1. An 0805 sized capacitor is recommended for system initial bring-up.
Figure 63. SerDes PLL Power Supply Filter
Note the following:
•
•
AV _SRDSn should be a filtered version of SV _SRDSn.
DD DD
Signals on the SerDesn interface are fed from the XV _SRDSn power plane.
DD
21.3 Decoupling Recommendations
Due to large address and data buses, and high operating frequencies, the device can generate transient
power surges and high frequency noise in its power supply, especially while driving large capacitive loads.
This noise must be prevented from reaching other components in the MPC8572E system, and the device
itself requires a clean, tightly regulated source of power. Therefore, it is recommended that the system
designer place at least one decoupling capacitor at each V , TV , BV , OV , GV , and LV pin
DD
DD
DD
DD
DD
DD
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
126
FREESCALE [ Freescale ]
