PCI Express
parasitic characteristics that cause the real PCI Express component to vary in impedance from the
compliance/test measurement load. The input receiver eye diagram is implementation specific and is not
specified. Rx component designer should provide additional margin to adequately compensate for the
degraded minimum receiver eye diagram (shown in Figure 47) expected at the input receiver based on an
adequate combination of system simulations and the return loss measured looking into the Rx package and
silicon. The Rx eye diagram must be aligned in time using the jitter median to locate the center of the eye
diagram.
The eye diagram must be valid for any 250 consecutive UIs.
A recovered Tx UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is
created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the Tx
UI.
NOTE
The reference impedance for return loss measurements is 50. to ground for
both the D+ and D– line (that is, as measured by a Vector Network Analyzer
with 50. probes—see Figure 48). Note that the series capacitors, C
are optional for the return loss measurement.
,
PEACCTX
VRX-DIFF = 0 mV
(D+ D– Crossing Point)
VRX-DIFF = 0 mV
(D+ D– Crossing Point)
VRX-DIFFp-p-MIN > 175 mV
0.4 UI = TRX-EYE-MIN
Figure 47. Minimum Receiver Eye Timing and Voltage Compliance Specification
™
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
72
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