Enhanced Secure Digital Host Controller (eSDHC)
LCLK
T1
T2
T3
T4
t
LBKHOV
GPCM Mode Output Signals:
LCS[0:7]/LWE[0:3]
t
LBIVKH
UPM Mode Input Signal:
LUPWAIT
t
LBIVKH
t
LBIXKH
t
LBIXKH
t
LBKHOZ
Input Signals:
LAD[0:31]
t
LBKHOV
UPM Mode Output Signals:
LCS[0:7]/LBS[0:1]/LGPL[0:5]
t
LBKHOV
t
LBKHOZ
Output (Data) Signals:
LAD[0:31]/LDP[0:3]
Output (Address) Signal:
LAD[0:31]
t
LBKHOV
t
LBKHOZ
Figure 29. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4 (PLL Bypass Mode)
11 Enhanced Secure Digital Host Controller (eSDHC)
This section describes the DC and AC electrical specifications for the eSDHC (SD/MMC) interface of the
MPC8378E.
The eSDHC controller always uses the falling edge of the SD_CLK in order to drive the
SD_DAT[0:3]/CMD as outputs and sample the SD_DAT[0:3] as inputs. This behavior is true for both full-
and high-speed modes.
Note that this is a non-standard implementation, as the SD card specification assumes that in high-speed
mode, that data will be driven at the rising edge of the clock.
MPC8378E PowerQUICC
™
II Pro Processor Hardware Specifications, Rev. 2
48
Freescale Semiconductor
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
