Freescale Semiconductor, Inc.
Table 2-1 Port Signal Functions
Port/Bit
Single-Chip and
Bootstrap Mode
Expanded and
Special Test Mode
PA0
PA1
PA0/IC3
PA1/IC2
PA2/IC1
PA2
PA3
PA3/OC5/IC4/OC1
PA4/OC4/OC1
PA5/OC3/OC1
PA6/OC2/OC1
PA7/PAI/OC1
PA4
PA5
PA6
PA7
PB[7:0]
PC[7:0]
PD0
PB[7:0]
PC[7:0]
ADDR[15:8]
DATA[7:0]
PD0/RxD
PD1/TxD
PD1
PD2
PD2/MISO
PD3/MOSI
PD4/SCK
PD3
PD4
PD5
PD5/SS
PE[7:0]
PF[7:0]
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
PE[7:0]/AN[7:0]
PF[7:0]
ADDR[7:0]
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
PG4/CSIO2
PG5/CSIO1
PG6/CSGEN
PG7/CSPROG
2.11.1 Port A
Port A is an 8-bit general-purpose I/O port with a data register (PORTA) and a data
direction register (DDRA). Port A pins share functions with the 16-bit timer system.
PORTA can be read at any time. Inputs return the pin level; outputs return the pin driv-
er input level. If written, PORTA stores the data in internal latches. It drives the pins
only if they are configured as outputs. Writes to PORTA do not change the pin state
when the pins are configured for timer output compares.
Out of reset, port A pins [7:0] are general-purpose high-impedance inputs. When the
timer functions associated with these pins are disabled, the bits in DDRA govern the
I/O state of the associated pin. For further information, refer to SECTION 6 PARAL-
LEL INPUT/OUTPUT.
NOTE
When using the information about port functions, do not confuse pin
function with the electrical state of the pin at reset. All general-pur-
pose I/O pins configured as inputs at reset are in a high-impedance
state. Port data registers reflect the logic state of the port at reset.
The pin function is mode dependent.
PIN DESCRIPTIONS
TECHNICAL DATA
2-7
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