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MCHC11F1CFNE2 参数 Datasheet PDF下载

MCHC11F1CFNE2图片预览
型号: MCHC11F1CFNE2
PDF下载: 下载PDF文件 查看货源
内容描述: 技术参数 [Technical Data]
分类和应用: 外围集成电路可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件页数/大小: 158 页 / 993 K
品牌: FREESCALE [ Freescale ]
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Freescale Semiconductor, Inc.  
2.2 Reset (RESET)  
An active low bidirectional control signal, RESET, acts as an input to initialize the MCU  
to a known start-up state. It also acts as an open-drain output to indicate that an inter-  
nal failure has been detected in either the clock monitor or COP watchdog circuit. The  
CPU distinguishes between internal and external reset conditions by sensing whether  
the reset pin rises to a logic one in less than two E-clock cycles after a reset has oc-  
curred. It is not advisable to connect an external resistor-capacitor (RC) power-up de-  
lay circuit to the reset pin of M68HC11 devices because the circuit charge time  
constant can cause the device to misinterpret the type of reset that occurred. Refer to  
SECTION 5 RESETS AND INTERRUPTS for further information.  
Figure 2-3 illustrates a reset circuit that uses an external switch. Other circuits can be  
used, however, it is important to incorporate a low voltage interrupt (LVI) circuit to pre-  
vent operation at insufficient voltage levels which could result in erratic behavior or cor-  
ruption of RAM.  
V
DD  
V
DD  
V
DD  
MC34064  
2
4.7 kΩ  
IN  
1
MANUAL  
RESET SWITCH  
TO RESET  
OF M68HC11  
RESET  
4.7 kΩ  
4.7 kΩ  
GND  
3
MC34164  
2
1.0 µF  
IN  
RESET  
GND  
1
OPTIONAL POWER-ON DELAY  
AND MANUAL RESET SWITCH  
3
Figure 2-3 External Reset Circuit  
2.3 E-Clock Output (E)  
E is the output connection for the internally generated E clock. The signal from E is  
used as a timing reference. The frequency of the E-clock output is one fourth that of  
the input frequency at the EXTAL pin. When E-clock output is low, an internal process  
is taking place. When it is high, data is being accessed. All clocks, including the E  
clock, are halted when the MCU is in STOP mode. The E clock can be turned off in  
single-chip modes to reduce the effects of radio frequency interference (RFI). Refer to  
SECTION 9 TIMING SYSTEM.  
2.4 Crystal Driver and External Clock Input (XTAL, EXTAL)  
These two pins provide the interface for either a crystal or a CMOS-compatible clock  
to control the internal clock generator circuitry. Either a crystal oscillator or a CMOS  
compatible clock can be used. The resulting E-clock rate is the input frequency divided  
by four.  
PIN DESCRIPTIONS  
TECHNICAL DATA  
2-3  
For More Information On This Product,  
Go to: www.freescale.com  
 
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