Timer Module (TIM16B8CV2) Block Description
The pulse accumulator counter register reflect the number of pulses from the divided-by-64 clock since the
last reset.
NOTE
The timer prescaler generates the divided-by-64 clock. If the timer is not
active, there is no divided-by-64 clock.
14.5 Resets
The reset state of each individual bit is listed within Section 14.3, “Memory Map and Register Definition”
which details the registers and their bit fields.
14.6 Interrupts
This section describes interrupts originated by the TIM16B8CV2 block. Table 14-24 lists the interrupts
generated by the TIM16B8CV2 to communicate with the MCU.
Table 14-24. TIM16B8CV1 Interrupts
Offset
Interrupt
Vector1
Priority1
Source
Description
(1)
C[7:0]F
PAOVI
—
—
—
—
—
—
Timer Channel 7–0
Active high timer channel interrupts 7–0
Pulse Accumulator
Input
Active high pulse accumulator input interrupt
PAOVF
—
—
—
—
—
—
Pulse Accumulator
Overflow
Pulse accumulator overflow interrupt
Timer Overflow interrupt
TOF
Timer Overflow
1. Chip Dependent.
The TIM16B8CV2 uses a total of 11 interrupt vectors. The interrupt vector offsets and interrupt numbers
are chip dependent.
14.6.1 Channel [7:0] Interrupt (C[7:0]F)
This active high outputs will be asserted by the module to request a timer channel 7 – 0 interrupt to be
serviced by the system controller.
14.6.2 Pulse Accumulator Input Interrupt (PAOVI)
This active high output will be asserted by the module to request a timer pulse accumulator input interrupt
to be serviced by the system controller.
14.6.3 Pulse Accumulator Overflow Interrupt (PAOVF)
This active high output will be asserted by the module to request a timer pulse accumulator overflow
interrupt to be serviced by the system controller.
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
499
FREESCALE [ Freescale ]
