Timer Module (TIM16B8CV2) Block Description
Bus Clock
CLK[1:0]
channel 7 output
compare
PR[2:1:0]
PACLK
PACLK/256
PACLK/65536
MUX
TCRE
PRESCALER
CxI
TCNT(hi):TCNT(lo)
16-BIT COUNTER
CxF
CLEAR COUNTER
TOF
TOI
INTERRUPT
LOGIC
TOF
TE
CHANNEL 0
16-BIT COMPARATOR
TC0
C0F
C0F
CH. 0 CAPTURE
OM:OL0
IOC0 PIN
LOGIC
IOC0 PIN
TOV0
CH. 0COMPARE
EDGE
DETECT
EDG0A EDG0B
IOC0
C1F
CHANNEL 1
16-BIT COMPARATOR
TC1
C1F
CH. 1 CAPTURE
CH. 1 COMPARE
OM:OL1
TOV1
IOC1 PIN
LOGIC
IOC1 PIN
EDGE
DETECT
EDG1A EDG1B
CHANNEL2
IOC1
C7F
CHANNEL7
16-BIT COMPARATOR
TC7
C7F
CH.7 CAPTURE
PA INPUT
IOC7 PIN
LOGIC
OM:OL7
TOV7
IOC7 PIN
CH. 7 COMPARE
EDG7A
EDG7B
EDGE
DETECT
IOC7
PAOVF
PACNT(hi):PACNT(lo)
PEDGE
PAE
EDGE
DETECT
PACLK/65536
PACLK/256
16-BIT COUNTER
PACLK
PAMOD
INTERRUPT
REQUEST
INTERRUPT
LOGIC
PAIF
DIVIDE-BY-64
Bus Clock
PAOVI
PAI
PAIF
PAOVF
PAOVF
PAOVI
Figure 14-30. Detailed Timer Block Diagram
14.4.1 Prescaler
The prescaler divides the bus clock by 1,2,4,8,16,32,64 or 128. The prescaler select bits, PR[2:0], select
the prescaler divisor. PR[2:0] are in timer system control register 2 (TSCR2).
S12P-Family Reference Manual, Rev. 1.13
496
Freescale Semiconductor
FREESCALE [ Freescale ]
