欢迎访问ic37.com |
会员登录 免费注册
发布采购

MC9S12P64CFT 参数 Datasheet PDF下载

MC9S12P64CFT图片预览
型号: MC9S12P64CFT
PDF下载: 下载PDF文件 查看货源
内容描述: 微控制器 [Microcontrollers]
分类和应用: 微控制器外围集成电路时钟
文件页数/大小: 566 页 / 7414 K
品牌: FREESCALE [ Freescale ]
 浏览型号MC9S12P64CFT的Datasheet PDF文件第297页浏览型号MC9S12P64CFT的Datasheet PDF文件第298页浏览型号MC9S12P64CFT的Datasheet PDF文件第299页浏览型号MC9S12P64CFT的Datasheet PDF文件第300页浏览型号MC9S12P64CFT的Datasheet PDF文件第302页浏览型号MC9S12P64CFT的Datasheet PDF文件第303页浏览型号MC9S12P64CFT的Datasheet PDF文件第304页浏览型号MC9S12P64CFT的Datasheet PDF文件第305页  
Freescale’s Scalable Controller Area Network (S12MSCANV3)  
8.4.5.7  
Disabled Mode  
The MSCAN is in disabled mode out of reset (CANE=0). All module clocks are stopped for power saving,  
however the register map can still be accessed as specified.  
8.4.5.8  
Programmable Wake-Up Function  
The MSCAN can be programmed to wake up from sleep or power down mode as soon as CAN bus activity  
is detected (see control bit WUPE in MSCAN Control Register 0 (CANCTL0). The sensitivity to existing  
CAN bus action can be modified by applying a low-pass filter function to the RXCAN input line (see  
control bit WUPM in Section 8.3.2.2, “MSCAN Control Register 1 (CANCTL1)”).  
This feature can be used to protect the MSCAN from wake-up due to short glitches on the CAN bus lines.  
Such glitches can result from—for example—electromagnetic interference within noisy environments.  
8.4.6  
Reset Initialization  
The reset state of each individual bit is listed in Section 8.3.2, “Register Descriptions,” which details all  
the registers and their bit-fields.  
8.4.7  
Interrupts  
This section describes all interrupts originated by the MSCAN. It documents the enable bits and generated  
flags. Each interrupt is listed and described separately.  
8.4.7.1  
Description of Interrupt Operation  
The MSCAN supports four interrupt vectors (see Table 8-39), any of which can be individually masked  
(for details see Section 8.3.2.6, “MSCAN Receiver Interrupt Enable Register (CANRIER)” to  
Section 8.3.2.8, “MSCAN Transmitter Interrupt Enable Register (CANTIER)”).  
NOTE  
The dedicated interrupt vector addresses are defined in the Resets and  
Interrupts chapter.  
Table 8-39. Interrupt Vectors  
Interrupt Source  
CCR Mask  
Local Enable  
CANRIER (WUPIE)  
Wake-Up Interrupt (WUPIF)  
Error Interrupts Interrupt (CSCIF, OVRIF)  
Receive Interrupt (RXF)  
I bit  
I bit  
I bit  
I bit  
CANRIER (CSCIE, OVRIE)  
CANRIER (RXFIE)  
Transmit Interrupts (TXE[2:0])  
CANTIER (TXEIE[2:0])  
8.4.7.2  
Transmit Interrupt  
At least one of the three transmit buffers is empty (not scheduled) and can be loaded to schedule a message  
for transmission. The TXEx flag of the empty message buffer is set.  
S12P-Family Reference Manual, Rev. 1.13  
Freescale Semiconductor  
301  
 复制成功!