S12 Clock, Reset and Power Management Unit (S12CPMU)
7.4.2
Startup from Reset
An example of startup of clock system from Reset is given in Figure 7-31.
Figure 7-31. Startup of clock system after Reset
System
Reset
768 cycles
VCORST
f
=32 MHz
f
=16MHz
f
increasing
PLL
PLL
f
PLL
PLLCLK
LOCK
) (
t
lock
SYNDIV
$1F (default target f
$03 (default target f
reset state
=64MHz)
VCO
POSTDIV
=f
/4 = 16MHz)
$01
PLL VCO
example change
of POSTDIV
CPU
vector fetch, program execution
7.4.3
Stop Mode using PLLCLK as Bus Clock
An example of what happens going into Stop Mode and exiting Stop Mode after an interrupt is shown in
Figure 7-32. Disable PLL Lock interrupt (LOCKIE=0) before going into Stop Mode.
Figure 7-32. Stop Mode using PLLCLK as Bus Clock
wakeup
interrupt continue execution
execution
STOP instruction
CPU
t
STP_REC
PLLCLK
LOCK
t
lock
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
239
FREESCALE [ Freescale ]
