S12 Clock, Reset and Power Management Unit (S12CPMU)
7.3.2.21 S12CPMU Oscillator Register (CPMUOSC)
This registers configures the external oscillator (OSCLCP).
0x02FA
7
6
5
4
3
2
1
0
R
W
0
OSCE
OSCBW
OSCFILT[4:0]
Reset
0
0
0
0
0
0
0
0
Figure 7-28. S12CPMU Oscillator Register (CPMUOSC)
Read: Anytime
Write: If PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register), then write anytime.
Else write has no effect.
NOTE.
Write to this register clears the LOCK and UPOSC status bits.
NOTE.
If the chosen VCOCLK-to-OSCCLK ratio divided by two is not an integer
number, then the filter can not be used and the OSCFILT[4:0] bits must be
set to 0.
Table 7-22. CPMUOSC Field Descriptions
Field
Description
7
Oscillator Enable Bit — This bit enables the external oscillator (OSCLCP). The UPOSC status bit in the
CPMUFLG register indicates when the oscillation is stable and OSCCLK can be selected as Bus Clock or source
of the COP or RTI. A loss of oscillation will lead to a clock monitor reset.
0 External oscillator is disabled.
OSCE
REFCLK for PLL is IRCCLK.
1 External oscillator is enabled.Clock monitor is enabled.
REFCLK for PLL is the external oscillator clock divided by REFDIV.
Note: When starting up the external oscillator (either by programming OSCE bit to 1 or on exit from Full Stop
Mode with OSCE bit is already 1) the software must wait for a minimum time equivalent to the startup-time
of the external oscillator tUPOSC before entering Pseudo Stop Mode.
6
Oscillator Filter Bandwidth Bit — If the VCOCLK frequency exceeds 25 MHz wide bandwidth must be
selected.The Oscillator Filter is described in more detail at Section 7.4.5.2, “The Adaptive Oscillator Filter.
0 Oscillator filter bandwidth is narrow (window for expected OSCCLK edge is one VCOCLK cycle).
1 Oscillator filter bandwidth is wide (window for expected OSCCLK edge is three VCOCLK cycles).
OSCBW
4-0
Oscillator Filter Bits — When using the oscillator a noise filter can be enabled, which filters noise from the
OSCFILT OSCCLK and detects if the OSCCLK is qualified or not (quality status shown by bit UPOSC).
The fVCO -to- f OSC ratio divided by two must be an integer value. The OSCFILT[4:0] bits must be set to the
calculated integer value to enable the oscillator filter).
0x0000 Oscillator Filter disabled.
else Oscillator Filter enabled:
S12P-Family Reference Manual, Rev. 1.13
234
Freescale Semiconductor
FREESCALE [ Freescale ]
