S12S Debug Module (S12SDBGV2)
Field2 Bits in Normal and Loop1 Modes
Bit 3
CSD
Bit 2
CVA
Bit 1
Bit 0
PC17
PC16
Figure 6-26. Information Bits PCH
Table 6-39. PCH Field Descriptions
Description
Bit
3
Source Destination Indicator — In Normal and Loop1 mode this bit indicates if the corresponding stored
CSD
address is a source or destination address. This bit has no meaning in Compressed Pure PC mode.
0 Source Address
1 Destination Address
2
CVA
Vector Indicator — In Normal and Loop1 mode this bit indicates if the corresponding stored address is a vector
address. Vector addresses are destination addresses, thus if CVA is set, then the corresponding CSD is also set.
This bit has no meaning in Compressed Pure PC mode.
0 Non-Vector Destination Address
1 Vector Destination Address
1
Program Counter bit 17— In Normal and Loop1 mode this bit corresponds to program counter bit 17.
Program Counter bit 16— In Normal and Loop1 mode this bit corresponds to program counter bit 16.
PC17
0
PC16
6.4.5.4
Trace Buffer Organization (Compressed Pure PC mode)
Table 6-40. Trace Buffer Organization Example (Compressed PurePC mode)
2-bits
6-bits
6-bits
6-bits
Line
Number
Mode
Field 3
00
Field 2
Field 1
Field 0
Line 1
Line 2
Line 3
Line 4
Line 5
Line 6
PC1 (Initial 18-bit PC Base Address)
11
PC4
0
PC3
PC2
PC5
01
0
Compressed
Pure PC Mode
00
PC6 (New 18-bit PC Base Address)
PC8
10
0
PC7
00
PC9 (New 18-bit PC Base Address)
NOTE
Configured for end aligned triggering in compressed PurePC mode, then
after rollover it is possible that the oldest base address is overwritten. In this
case all entries between the pointer and the next base address have lost their
base address following rollover. For example in Table 6-40 if one line of
rollover has occurred, Line 1, PC1, is overwritten with a new entry. Thus the
entries on Lines 2 and 3 have lost their base address. For reconstruction of
program flow the first base address following the pointer must be used, in
the example, Line 4. The pointer points to the oldest entry, Line 2.
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
185