S12S Debug Module (S12SDBGV2)
6.4.5.2.1
Normal Mode
In Normal Mode, change of flow (COF) program counter (PC) addresses are stored.
COF addresses are defined as follows:
•
•
•
•
Source address of taken conditional branches (long, short, bit-conditional, and loop primitives)
Destination address of indexed JMP, JSR, and CALL instruction
Destination address of RTI, RTS, and RTC instructions
Vector address of interrupts, except for BDM vectors
LBRA, BRA, BSR, BGND as well as non-indexed JMP, JSR, and CALL instructions are not classified as
change of flow and are not stored in the trace buffer.
Stored information includes the full 18-bit address bus and information bits, which contains a
source/destination bit to indicate whether the stored address was a source address or destination address.
NOTE
When a COF instruction with destination address is executed, the
destination address is stored to the trace buffer on instruction completion,
indicating the COF has taken place. If an interrupt occurs simultaneously
then the next instruction carried out is actually from the interrupt service
routine. The instruction at the destination address of the original program
flow gets executed after the interrupt service routine.
In the following example an IRQ interrupt occurs during execution of the
indexed JMP at address MARK1. The BRN at the destination (SUB_1) is
not executed until after the IRQ service routine but the destination address
is entered into the trace buffer to indicate that the indexed JMP COF has
taken place.
LDX
JMP
NOP
#SUB_1
0,X
MARK1
MARK2
; IRQ interrupt occurs during execution of this
;
SUB_1
ADDR1
BRN
*
; JMP Destination address TRACE BUFFER ENTRY 1
; RTI Destination address TRACE BUFFER ENTRY 3
;
NOP
DBNE
A,PART5
; Source address TRACE BUFFER ENTRY 4
IRQ_ISR LDAB
#$F0
VAR_C1
; IRQ Vector $FFF2 = TRACE BUFFER ENTRY 2
;
STAB
RTI
The execution flow taking into account the IRQ is as follows
LDX
#SUB_1
MARK1
IRQ_ISR LDAB
JMP
0,X
#$F0
VAR_C1
;
;
STAB
RTI
;
SUB_1
ADDR1
BRN
NOP
DBNE
*
;
;
A,PART5
S12P-Family Reference Manual, Rev. 1.13
182
Freescale Semiconductor
FREESCALE [ Freescale ]
