S12S Debug Module (S12SDBGV2)
access causes a match. Thus if configured for a byte access of a particular address, a word access covering
the same address does not lead to match.
Assuming the access direction is not qualified (RWE=0), for simplicity, the size access considerations are
shown in Table 6-33.
Table 6-33. Comparator B Access Size Considerations
Condition For Valid Match
Comp B Address RWE SZE
SZ8
Examples
Word and byte accesses of ADDR[n]
ADDR[n](1)
ADDR[n]
ADDR[n]
0
0
0
0
1
1
X
MOVB #$BYTE ADDR[n]
MOVW #$WORD ADDR[n]
Word accesses of ADDR[n] only
Byte accesses of ADDR[n] only
0
1
MOVW #$WORD ADDR[n]
LDD ADDR[n]
MOVB #$BYTE ADDR[n]
LDAB ADDR[n]
1. A word access of ADDR[n-1] also accesses ADDR[n] but does not generate a match.
The comparator address register must contain the exact address from the code.
Access direction can also be used to qualify a match for Comparator B in the same way as described for
Comparator C in Table 6-32.
6.4.2.1.3
Comparator A
Comparator A offers address, direction (R/W), access size (word/byte) and data bus comparison.
Table 6-34 lists access considerations with data bus comparison. On word accesses the data byte of the
lower address is mapped to DBGADH. Access direction can also be used to qualify a match for
Comparator A in the same way as described for Comparator C in Table 6-32.
Table 6-34. Comparator A Matches When Accessing ADDR[n]
DBGADHM,
DBGADLM
Access
DH=DBGADH, DL=DBGADL
SZE
SZ
Comment
0
X
$0000
Byte
No databus comparison
Word
0
X
$FF00
Byte, data(ADDR[n])=DH
Match data( ADDR[n])
Word, data(ADDR[n])=DH, data(ADDR[n+1])=X
0
0
0
0
1
1
1
1
1
1
X
X
X
X
0
0
0
0
1
1
$00FF
$00FF
$FFFF
$FFFF
$0000
$00FF
$FF00
$FFFF
$0000
$FF00
Word, data(ADDR[n])=X, data(ADDR[n+1])=DL
Byte, data(ADDR[n])=X, data(ADDR[n+1])=DL
Word, data(ADDR[n])=DH, data(ADDR[n+1])=DL
Byte, data(ADDR[n])=DH, data(ADDR[n+1])=DL
Word
Match data( ADDR[n+1])
Possible unintended match
Match data( ADDR[n], ADDR[n+1])
Possible unintended match
No databus comparison
Word, data(ADDR[n])=X, data(ADDR[n+1])=DL
Word, data(ADDR[n])=DH, data(ADDR[n+1])=X
Word, data(ADDR[n])=DH, data(ADDR[n+1])=DL
Byte
Match only data at ADDR[n+1]
Match only data at ADDR[n]
Match data at ADDR[n] & ADDR[n+1]
No databus comparison
Byte, data(ADDR[n])=DH
Match data at ADDR[n]
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
177
FREESCALE [ Freescale ]
