Background Debug Module (S12SBDMV1)
8 Bits
AT ~16 TC/Bit
16 Bits
AT ~16 TC/Bit
150-BC
Delay
16 Bits
AT ~16 TC/Bit
Hardware
Read
Next
Command
Command
Command
Command
Command
Command
Address
Data
150-BC
Delay
Hardware
Write
Next
Command
Address
Data
48-BC
DELAY
Firmware
Read
Next
Command
Data
36-BC
DELAY
Firmware
Write
Next
Command
Data
76-BC
Delay
GO,
TRACE
Next
Command
BC = Bus Clock Cycles
TC = Target Clock Cycles
Figure 5-6. BDM Command Structure
5.4.6
BDM Serial Interface
The BDM communicates with external devices serially via the BKGD pin. During reset, this pin is a mode
select input which selects between normal and special modes of operation. After reset, this pin becomes
the dedicated serial interface pin for the BDM.
The BDM serial interface is timed based on the VCO clock (please refer to the CPMU Block Guide for
more details), which gets divided by 8. This clock will be referred to as the target clock in the following
explanation.
The BDM serial interface uses a clocking scheme in which the external host generates a falling edge on
the BKGD pin to indicate the start of each bit time. This falling edge is sent for every bit whether data is
transmitted or received. Data is transferred most significant bit (MSB) first at 16 target clock cycles per
bit. The interface times out if 512 clock cycles occur between falling edges from the host.
The BKGD pin is a pseudo open-drain pin and has an weak on-chip active pull-up that is enabled at all
times. It is assumed that there is an external pull-up and that drivers connected to BKGD do not typically
drive the high level. Since R-C rise time could be unacceptably long, the target system and host provide
brief driven-high (speedup) pulses to drive BKGD to a logic 1. The source of this speedup pulse is the host
for transmit cases and the target for receive cases.
The timing for host-to-target is shown in Figure 5-7 and that of target-to-host in Figure 5-8 and
Figure 5-9. All four cases begin when the host drives the BKGD pin low to generate a falling edge. Since
the host and target are operating from separate clocks, it can take the target system up to one full clock
cycle to recognize this edge. The target measures delays from this perceived start of the bit time while the
host measures delays from the point it actually drove BKGD low to start the bit up to one target clock cycle
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
143
FREESCALE [ Freescale ]
