Central Processor Unit (CPU)
Instruction Set Summary
7.7 Instruction Set Summary
Table 7-1 provides a summary of the M68HC08 instruction set.
Table 7-1. Instruction Set Summary (Sheet 1 of 7)
Effect
Source
Form
on CCR
Operation
Description
V H I N Z C
ADC #opr
IMM
DIR
EXT
IX2
A9 ii
B9 dd
C9 hh ll
D9 ee ff
E9 ff
2
3
4
4
3
2
4
5
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
Add with Carry
A ← (A) + (M) + (C)
ꢀ
ꢀ
ꢀ
–
–
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
IX1
IX
SP1
SP2
F9
ADC opr,SP
ADC opr,SP
9EE9 ff
9ED9 ee ff
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
ADD opr,SP
ADD opr,SP
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
AB ii
BB dd
CB hh ll
DB ee ff
EB ff
FB
9EEB ff
9EDB ee ff
2
3
4
4
3
2
4
5
Add without Carry
A ← (A) + (M)
ꢀ
ꢀ
AIS #opr
AIX #opr
Add Immediate Value (Signed) to SP
Add Immediate Value (Signed) to H:X
–
–
–
–
–
–
–
–
–
–
– IMM
– IMM
A7 ii
AF ii
2
2
SP ← (SP) + (16 « M)
H:X ← (H:X) + (16 « M)
AND #opr
AND opr
IMM
DIR
EXT
A4 ii
B4 dd
C4 hh ll
D4 ee ff
E4 ff
2
3
4
4
3
2
4
5
AND opr
AND opr,X
AND opr,X
AND ,X
AND opr,SP
AND opr,SP
IX2
Logical AND
A ← (A) & (M)
0
–
–
–
–
ꢀ
ꢀ
ꢀ
ꢀ
–
IX1
IX
SP1
SP2
F4
9EE4 ff
9ED4 ee ff
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
ASL opr,SP
DIR
INH
38 dd
48
4
1
1
4
3
5
Arithmetic Shift Left
(Same as LSL)
INH
58
C
0
ꢀ
ꢀ
IX1
68 ff
78
b7
b7
b0
b0
IX
SP1
9E68 ff
ASR opr
ASRA
ASRX
ASR opr,X
ASR opr,X
ASR opr,SP
DIR
INH
37 dd
47
4
1
1
4
3
5
INH
57
C
Arithmetic Shift Right
ꢀ
–
–
–
–
ꢀ
ꢀ
ꢀ
IX1
67 ff
77
IX
SP1
9E67 ff
BCC rel
Branch if Carry Bit Clear
PC ← (PC) + 2 + rel ? (C) = 0
–
–
–
– REL
24 rr
3
DIR (b0) 11 dd
DIR (b1) 13 dd
DIR (b2) 15 dd
DIR (b3) 17 dd
DIR (b4) 19 dd
DIR (b5) 1B dd
DIR (b6) 1D dd
DIR (b7) 1F dd
4
4
4
4
4
4
4
4
BCLR n, opr
Clear Bit n in M
Mn ← 0
–
–
–
–
–
–
BCS rel
BEQ rel
Branch if Carry Bit Set (Same as BLO)
Branch if Equal
PC ← (PC) + 2 + rel ? (C) = 1
PC ← (PC) + 2 + rel ? (Z) = 1
–
–
–
–
–
–
–
–
–
–
– REL
– REL
25 rr
27 rr
3
3
MC68HC908MR32 • MC68HC908MR16 — Rev. 6.0
MOTOROLA Central Processor Unit (CPU)
Data Sheet
93
FREESCALE [ Freescale ]
