Clock Generator Module (CGM)
6.5.3 PLL Multiplier Select Registers
The PLL multiplier select registers (PMSH and PMSL) contain the programming information for the
modulo feedback divider.
Address:
$0038
Bit 7
0
6
0
5
0
4
0
3
MUL11
0
2
MUL10
0
1
MUL9
0
Bit 0
MUL8
0
Read:
Write:
Reset:
0
0
0
0
= Unimplemented
Figure 6-6. PLL Multiplier Select Register High (PMSH)
Address:
$0039
Bit 7
MUL7
0
6
MUL6
1
5
MUL5
0
4
MUL4
0
3
MUL3
0
2
MUL2
0
1
MUL1
0
Bit 0
MUL0
0
Read:
Write:
Reset:
Figure 6-7. PLL Multiplier Select Register Low (PMSL)
MUL[11:0] — Multiplier Select Bits
These read/write bits control the modulo feedback divider that selects the VCO frequency multiplier N.
(See 6.3.3 PLL Circuits and 6.3.6 Programming the PLL.) A value of $0000 in the multiplier select
registers configure the modulo feedback divider the same as a value of $0001. Reset initializes the
registers to $0040 for a default multiply value of 64.
NOTE
The multiplier select bits have built-in protection such that they cannot be
written when the PLL is on (PLLON = 1).
6.5.4 PLL VCO Range Select Register
The PLL VCO range select register (PMRS) contains the programming information required for the
hardware configuration of the VCO.
Address:
$003A
Bit 7
6
VRS6
1
5
VRS5
0
4
VRS4
0
3
VRS3
0
2
VRS2
0
1
VRS1
0
Bit 0
VRS0
0
Read:
Write:
Reset:
VRS7
0
Figure 6-8. PLL VCO Range Select Register (PMRS)
VRS[7:0] — VCO Range Select Bits
These read/write bits control the hardware center-of-range linear multiplier L which, in conjunction with
E (See 6.3.3 PLL Circuits, 6.3.6 Programming the PLL, and 6.5.1 PLL Control Register.), controls the
hardware center-of-range frequency, f
. VRS[7:0] cannot be written when the PLLON bit in the
VRS
PCTL is set. (See 6.3.7 Special Programming Exceptions.) A value of $00 in the VCO range select
MC68HC908AP Family Data Sheet, Rev. 4
92
Freescale Semiconductor
FREESCALE [ Freescale ]
