Clock Generator Module (CGM)
1. Choose the desired bus frequency, f
solve for the other.
, or the desired VCO frequency, f
; and then
VCLKDES
BUSDES
The relationship between f
and f
is governed by the equation:
BUS
VCLK
P
P
f
= 2 × f
= 2 × 4 × f
VCLK
CGMPCLK
BUS
where P is the power of two multiplier, and can be 0, 1, 2, or 3
2. Choose a practical PLL reference frequency, f
the reference is 32.768kHz and R = 1.
, and the reference clock divider, R. Typically,
RCLK
Frequency errors to the PLL are corrected at a rate of f
/R. For stability and lock time reduction,
RCLK
this rate must be as fast as possible. The VCO frequency must be an integer multiple of this rate.
The relationship between the VCO frequency, f
, and the reference frequency, f
, is
VCLK
RCLK
P
2 N
= ----------- (f
R
f
)
VCLK
RCLK
where N is the integer range multiplier, between 1 and 4095.
In cases where desired bus frequency has some tolerance, choose f
to a value determined
RCLK
either by other module requirements (such as modules which are clocked by CGMXCLK), cost
requirements, or ideally, as high as the specified range allows. See Chapter 22 Electrical
Specifications.
Choose the reference divider, R = 1.
When the tolerance on the bus frequency is tight, choose f
to an integer divisor of f
,
RCLK
BUSDES
and R = 1. If f
cannot meet this requirement, use the following equation to solve for R with
RCLK
practical choices of f
, and choose the f
that gives the lowest R.
RCLK
RCLK
f
f
VCLKDES
⎛
⎜
⎝
⎞
⎟
⎠
⎛
⎜
⎝
⎞
⎟
⎠
⎧
⎨
⎩
⎫
⎬
⎭
VCLKDES
R = round R
×
– integer
-------------------------
-------------------------
MAX
f
f
RCLK
RCLK
3. Calculate N:
R × f
⎛
⎜
⎝
⎞
VCLKDES
N = round
------------------------------------
⎟
⎠
P
f
× 2
RCLK
4. Calculate and verify the adequacy of the VCO and bus frequencies f
and f
.
VCLK
BUS
P
2 N
R
f
= ----------- (f
)
RCLK
VCLK
f
VCLK
P
f
=
-----------
BUS
2 × 4
MC68HC908AP Family Data Sheet, Rev. 4
84
Freescale Semiconductor
FREESCALE [ Freescale ]
