Chapter 6
Clock Generator Module (CGM)
6.1 Introduction
This section describes the clock generator module (CGM). The CGM generates the base clock signal,
CGMOUT, which is based on either the oscillator clock divided by two or the divided phase-locked loop
(PLL) clock, CGMPCLK, divided by two. CGMOUT is the clock from which the SIM derives the system
clocks, including the bus clock, which is at a frequency of CGMOUT 2.
The PLL is a frequency generator designed for use with a low frequency crystal (typically 32.768kHz) to
generate a base frequency and dividing to a maximum bus frequency of 8MHz.
6.2 Features
Features of the CGM include:
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Phase-locked loop with output frequency in integer multiples of an integer dividend of the crystal
reference
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Low-frequency crystal operation with low-power operation and high-output frequency resolution
Programmable prescaler for power-of-two increases in frequency
Programmable hardware voltage-controlled oscillator (VCO) for low-jitter operation
Automatic bandwidth control mode for low-jitter operation
Automatic frequency lock detector
CPU interrupt on entry or exit from locked condition
Configuration register bit to allow oscillator operation during stop mode
6.3 Functional Description
The CGM consists of three major sub-modules:
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Oscillator module — The oscillator module generates the constant reference frequency clock,
CGMRCLK (buffered CGMXCLK).
Phase-locked loop (PLL) — The PLL generates the programmable VCO frequency clock,
CGMVCLK, and the divided VCO clock, CGMPCLK.
Base clock selector circuit — This software-controlled circuit selects either CGMXCLK divided by
two or the divided VCO clock, CGMPCLK, divided by two as the base clock, CGMOUT. The SIM
derives the system clocks from either CGMOUT or CGMXCLK.
Figure 6-1 shows the structure of the CGM.
Figure 6-2 is a summary of the CGM registers.
MC68HC908AP Family Data Sheet, Rev. 4
Freescale Semiconductor
79
FREESCALE [ Freescale ]
