Timer Interface Module (TIM)
9.4 Functional Description
Figure 9-1 shows the structure of the TIM. The central component of the TIM is the 16-bit TIM counter
that can operate as a free-running counter or a modulo up-counter. The TIM counter provides the timing
reference for the input capture and output compare functions. The TIM counter modulo registers,
TMODH:TMODL, control the modulo value of the TIM counter. Software can read the TIM counter value
at any time without affecting the counting sequence.
The two TIM channels (per timer) are programmable independently as input capture or output compare
channels.
PRESCALER SELECT
INTERNAL
PRESCALER
BUS CLOCK
TSTOP
PS2
PS1
PS0
TRST
16-BIT COUNTER
TOF
INTERRUPT
LOGIC
TOIE
16-BIT COMPARATOR
TMODH:TMODL
TOV0
ELS0B
ELS0A
PORT
LOGIC
CHANNEL 0
16-BIT COMPARATOR
TCH0H:TCH0L
CH0MAX
T[1,2]CH0
CH0F
INTERRUPT
LOGIC
16-BIT LATCH
MS0A
CH0IE
MS0B
CH1F
TOV1
ELS0B
ELS0A
PORT
LOGIC
CHANNEL 1
16-BIT COMPARATOR
TCH1H:TCH1L
CH1MAX
T[1,2]CH1
INTERRUPT
LOGIC
CH01IE
CH1IE
16-BIT LATCH
MS0A
Figure 9-1. TIM Block Diagram
Figure 9-2 summarizes the timer registers.
NOTE
References to either timer 1 or timer 2 may be made in the following text by
omitting the timer number. For example, TSC may generically refer to both
T1SC and T2SC.
MC68HC908AP Family Data Sheet, Rev. 4
136
Freescale Semiconductor
FREESCALE [ Freescale ]
