Ordering Information
Rev. No.
Table 20. Document Revision History (continued)
Substantive Change(s)
1.1
Removed reference to Note 4 for DTI signals in Table 15 and Table 16: these signals are unused in 60x
bus mode and must be pulled down (see Note 13); they are not ignored.
Improved precision of die and package dimensions in Figure 20 and Figure 21.
2
Corrected entries in Table 17 for 33 MHz and 50 MHz bus frequencies with multipliers of 24x and higher.
Corrected typographical errors in heatsink selection example in Section 9.8.3, “Heat Sink Selection
Example.”
Removed erroneous instances of PLL_EXT signal name and changed remaining instances of
PLL_CFG[0:3] to PLL_CFG[0:4]. (These were artifacts from older revisions; see entry for Rev 1.0.)
Corrected erroneous instances (artifacts) mentioning 1.6 V core voltage. Core voltage for devices
completely covered by this revision (and revisions 1.x) of this document is 1.3 V.
Corrected errors in PLL multipliers in Table 17: 32x and 25x are not supported ratios, 3x and 4x are
supported, 10.5x and 12.5x PLL settings were incorrect.
Replaced notes at bottom of Table 17 (erroneously missing in revisions 1.x).
Updated coplanarity specifications in Figure 20 and Figure 21 from 0.2 mm to 0.15 mm.
3
4
Added Revision G (Rev 3.4) devices to specifications.
Added new PowerPC trademarking information.
Added substrate capacitor information in Section 8.3, “Substrate Capacitors for the MPC7445, 360
CBGA,” and Section 8.6, “Substrate Capacitors for the MPC7455, 483 CBGA.”
Clarified maximum and typical L3 clock frequency in Section 5.2.3, “L3 Clock AC Specifications”; typical
L3 frequency now stated as 250 MHz based on changes to L3 AC timing.
Significantly changed L3 AC timing in Table 12 and Table 13. These changes reflect both updates
based on latest characterization and error corrections (effects of non-zero L3OH values were incorrectly
documented in earlier revisions of this document).
Clarified address bus pull-up resistor recommendations in Section 9.6, “Pull-Up/Pull-Down Resistor
Requirements.”
Added pull-up/pull-down recommendations for CKSTP_IN and PLL_CFG[0:4] to Section 9.6,
“Pull-Up/Pull-Down Resistor Requirements.”
Modified Table 9, Figure 5, and Figure 6 to more accurately show when the mode select inputs
(BMODE[0:1], L3VSEL, BVSEL) are sampled and AC timing requirements.
Figure 20 and Figure 22: Updated/corrected dimensions in mechanical drawings.
Document tempate update.
4.1
11 Ordering Information
Ordering information for the parts fully covered by this specification document is provided in Section 11.1, “Part
Numbers Fully Addressed by This Document.” Note that the individual part numbers correspond to a maximum
processor core frequency. For available frequencies, contact your local Freescale sales office. In addition to the
processor frequency, the part numbering scheme also includes an application modifier which may specify special
application conditions. Each part number also contains a revision level code which refers to the die mask revision
number. Section 11.2, “Part Numbers Not Fully Addressed by This Document,” lists the part numbers which do not
MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1
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