Pinout Listings
Notes
Table 15. Pinout Listing for the MPC7445, 360 CBGA Package (continued)
1
Signal Name
TBEN
Pin Number
Active
I/O
I/F Select
E1
F11
C6
B9
A4
L1
High
Low
High
High
High
Low
—
Input
Output
Input
Input
Output
Input
Input
Input
Input
Input
I/O
BVSEL
BVSEL
BVSEL
BVSEL
BVSEL
BVSEL
BVSEL
BVSEL
BVSEL
BVSEL
BVSEL
BVSEL
BVSEL
BVSEL
N/A
TBST
TCK
TDI
7
TDO
TEA
TEST[0:3]
TEST[4]
TMS
A12, B6, B10, E10
2
9
D10
—
F1
High
Low
Low
High
High
Low
—
7
TRST
TS
A5
7, 14
8
L4
TSIZ[0:2]
TT[0:4]
WT
G6, F7, E7
E5, E6, F6, E9, C5
D3
Output
I/O
Output
—
8
V
H8, H10, H12, J7, J9, J11, J13, K8, K10,
K12, K14, L7, L9, L11, L13, M8, M10, M12
DD
Notes:
1. OV supplies power to the processor bus, JTAG, and all control signals; and V supplies power to the processor
DD
DD
core and the PLL (after filtering to become AV ). To program the I/O voltage, connect BVSEL to either GND
DD
(selects 1.8 V) or to HRESET (selects 2.5 V). If used, the pulldown resistor should be less than 250 Ω. For actual
recommended value of V or supply voltages see Table 4.
in
2. These input signals are for factory use only and must be pulled up to OV for normal machine operation.
DD
3. These signals are for factory use only and must be left unconnected for normal machine operation.
4. Ignored in 60x bus mode.
5. This signal selects between MPX bus mode (asserted) and 60x bus mode (negated) and will be sampled at
HRESET going high.
6. This signal must be negated during reset, by pull-up to OV or negation by ¬HRESET (inverse of HRESET), to
DD
ensure proper operation.
7. Internal pull-up on die.
8. These pins require weak pull-up resistors (for example, 4.7 kΩ) to maintain the control signals in the negated state
after they have been actively negated and released by the MPC7445 and other bus masters.
9. These input signals are for factory use only and must be pulled down to GND for normal machine operation.
10.This pin can externally cause a performance monitor event. Counting of the event is enabled via software.
11.Unused address pins must be pulled down to GND.
12.This test signal is recommended to be tied to HRESET; however, other configurations will not adversely affect
performance.
13.These signals must be pulled down to GND if unused, or if the MPC7445 is in 60x bus mode.
14.This signal must be asserted during reset, by pull-down to GND or assertion by HRESET, to ensure proper
operation.
MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1
Freescale Semiconductor
37
FREESCALE [ Freescale ]
