Freescale Semiconductor, Inc.
FLASH-2 Memory
5.9 FLASH Block Protect Register
The block protect register for FLASH-2 is physically implemented as a
byte within the FLASH-1 memory. Refer to Figure 4-4. FLASH-2 Block
Protect Register (FLBPR2) for definition of this register. Each bit, when
programmed, protects a range of addresses in the FLASH-2 array.
5.10 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-
consumption standby modes.
5.10.1 Wait Mode
Putting the MCU into wait mode while the FLASH is in read mode does
not affect the operation of the FLASH memory directly, but there will not
be any memory activity since the CPU is inactive.
The WAIT instruction should not be executed while performing a
program or erase operation on the FLASH. When the MCU is put into
wait mode, the charge pump for the FLASH is disabled so that either a
program or erase operation will not continue. If the memory is in either
program mode (PGM = 1, HVEN = 1) or erase mode (ERASE = 1,
HVEN = 1), then it will remain in that mode during wait. Exit from wait
must now be done with a reset rather than an interrupt because if exiting
wait with an interrupt, the memory will not be in read mode and the
interrupt vector cannot be read from the memory.
5.10.2 Stop Mode
When the MCU is put into stop mode, if the FLASH is in read mode, it
will be put into low-power standby.
The STOP instruction should not be executed while performing a
program or erase operation on the FLASH. When the MCU is put into
stop mode, the charge pump for the FLASH is disabled so that either a
program or erase operation will not continue. If the memory is in either
program mode (PGM = 1, HVEN = 1) or erase mode (ERASE = 1,
Technical Data
MC68HC908AS60 — Rev. 1.0
FLASH-2 Memory
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